Datasheet

ManualsBrandsST ManualsDiscrete SemiconductorsMOSFET, N-Channel, 500V, 53A, 460W, ISOTOP

1/8May 2002

STE53NC50

N-CHANNEL 500V - 0.070Ω - 53A ISOTOP

PowerMesh™II MOSFET

(1) I

≤ 53A, di/dt≤100 A/µs, V

≤ 24V, Tj≤T

jMAX

TYPICAL R

(on) = 0.07 Ω

EXTREMELY HIGH dv/dt CAPABILITY

100% AVALANCHE TESTED

NEW HIGH VOLTAGE BENCHMARK

GATE CHARGE MINIMIZED

DESCRIPTION

The PowerMESH

™II is the evolution of the first

generation of MESH OVERLAY

™. The layout re-

finements introduced greatly improve the Ron*area

figure of merit while keeping the device at the lead-

ing edge for what concerns swithing speed, gate

charge and ruggedness.

APPLICATIONS

HIGH CURRENT, HIGH SPEED SWITCHING

SWITH MODE POWER SUPPLIES (SMPS)

DC-AC CONVERTERS FOR WELDING

EQUIPMENT AND UNINTERRUPTIBLE

POWER SUPPLIES AND MOTOR DRIVER

ABSOLUTE MAXIMUM RATINGS

(•)Pulse width limited by safe operating area

TYPE V

DSS

DS(on)

STE53NC50 500V < 0.08Ω 53 A

Symbol Parameter Value Unit

Drain-source Voltage (V

= 0)

500 V

DGR

Drain-gate Voltage (R

= 20 kΩ)

500 V

Gate- source Voltage ±30 V

Drain Current (continuos) at T

= 25°C

53 A

Drain Current (continuos) at T

= 100°C

33 A

(

)

Drain Current (pulsed) 212 A

TOT

Total Dissipation at T

= 25°C

460 W

Derating Factor 3.68 W/°C

dv/dt (1) Peak Diode Recovery voltage slope 3 V/ns

ISO

Insulation Winthstand Voltage (AC-RMS) 2500 V

stg

Storage Temperature – 65 to 150 °C

Max. Operating Junction Temperature 150 °C

ISOTOP

INTERNAL SCHEMATIC DIAGRAM

Summary of content (8 pages)

PAGE 1
STE53NC50 N-CHANNEL 500V - 0.070Ω - 53A ISOTOP PowerMesh™II MOSFET TYPE STE53NC50 n n n n n VDSS RDS(on) ID 500V < 0.08Ω 53 A TYPICAL RDS(on) = 0.07 Ω EXTREMELY HIGH dv/dt CAPABILITY 100% AVALANCHE TESTED NEW HIGH VOLTAGE BENCHMARK GATE CHARGE MINIMIZED DESCRIPTION The PowerMESH™II is the evolution of the first generation of MESH OVERLAY™.
PAGE 2
STE53NC50 THERMAL DATA Rthj-case Rthc-h Thermal Resistance Junction-case Max 0.272 °C/W Thermal Resistance Case-heatsink with Conductive Grease Applied 0.
PAGE 3
STE53NC50 ELECTRICAL CHARACTERISTICS (CONTINUED) SWITCHING ON Symbol td(on) tr Parameter Turn-on Delay Time Rise Time Qg Total Gate Charge Qgs Gate-Source Charge Qgd Gate-Drain Charge Test Conditions Min. VDD = 250V, ID = 26.5A RG = 4.7Ω VGS = 10V (see test circuit, Figure 3) VDD = 400V, ID = 53A, VGS = 10V Typ. Max. Unit 46 ns 70 ns 310 434 nC 46 nC 150 nC SWITCHING OFF Symbol tr(Voff) Parameter Off-voltage Rise Time tf Fall Time tc Cross-over Time Test Conditions Min.
PAGE 4
STE53NC50 Output Characteristics Transfer Characteristics Transconductance Static Drain-source On Resistance Gate Charge vs Gate-source Voltage Capacitance Variations 4/8
PAGE 5
STE53NC50 Normalized Gate Thereshold Voltage vs Temp.
PAGE 6
STE53NC50 Fig. 1: Unclamped Inductive Load Test Circuit Fig. 2: Unclamped Inductive Waveform Fig. 3: Switching Times Test Circuit For Resistive Load Fig. 4: Gate Charge test Circuit Fig.
PAGE 7
STE53NC50 ISOTOP MECHANICAL DATA mm DIM. MIN. A TYP. 11.8 inch MAX. MIN. TYP. MAX. 12.2 0.466 0.480 B 8.9 9.1 0.350 0.358 C 1.95 2.05 0.076 0.080 D 0.75 0.85 0.029 0.033 E 12.6 12.8 0.496 0.503 F 25.15 25.5 0.990 1.003 G 31.5 31.7 1.240 1.248 H 4 J 4.1 4.3 0.161 0.169 K 14.9 15.1 0.586 0.594 L 30.1 30.3 1.185 1.193 M 37.8 38.2 1.488 1.503 8.2 0.307 0.157 N 4 O 7.8 0.157 0.
PAGE 8
STE53NC50 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice.