STM32F051x4 STM32F051x6 STM32F051x8 ARM®-based 32-bit MCU, 16 to 64 KB Flash, 11 timers, ADC, DAC and communication interfaces, 2.0-3.6 V Datasheet - production data Features &"'! ® ® • Core: ARM 32-bit Cortex -M0 CPU, frequency up to 48 MHz • Memories – 16 to 64 Kbytes of Flash memory – 8 Kbytes of SRAM with HW parity checking • CRC calculation unit • Reset and power management – Digital and I/O supply: VDD = 2.0 V to 3.6 V – Analog supply: VDDA = from VDD to 3.
Contents STM32F051x4 STM32F051x6 STM32F051x8 Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3 Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.1 ARM®-Cortex®-M0 core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.
STM32F051x4 STM32F051x6 STM32F051x8 3.14.6 Contents SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.15 Real-time clock (RTC) and backup registers . . . . . . . . . . . . . . . . . . . . . . 23 3.16 Inter-integrated circuit interface (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.17 Universal synchronous/asynchronous receiver/transmitter (USART) . . . 25 3.
Contents 7 STM32F051x4 STM32F051x6 STM32F051x8 6.3.14 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 6.3.15 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 6.3.16 12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 6.3.17 DAC electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 6.3.
STM32F051x4 STM32F051x6 STM32F051x8 List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. Table 45.
List of tables Table 47. Table 48. Table 49. Table 50. Table 51. Table 52. Table 53. Table 54. Table 55. Table 56. Table 57. Table 58. Table 59. Table 60. Table 61. Table 62. Table 63. Table 64. Table 65. Table 66. Table 67. Table 68. Table 69. Table 70. Table 71. Table 72. Table 73. Table 74. Table 75. Table 76. 6/121 Downloaded from Arrow.com. STM32F051x4 STM32F051x6 STM32F051x8 I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
STM32F051x4 STM32F051x6 STM32F051x8 List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40. Figure 41.
List of figures Figure 49. Figure 50. Figure 51. Figure 52. Figure 53. Figure 54. Figure 55. 8/121 Downloaded from Arrow.com. STM32F051x4 STM32F051x6 STM32F051x8 LQFP32 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 Recommended footprint for LQFP32 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 LQFP32 package marking example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
STM32F051x4 STM32F051x6 STM32F051x8 1 Introduction Introduction This datasheet provides the ordering information and mechanical device characteristics of the STM32F051xx microcontrollers. This document should be read in conjunction with the STM32F0xxxx reference manual (RM0091). The reference manual is available from the STMicroelectronics website www.st.com. For information on the ARM® Cortex®-M0 core, please refer to the Cortex®-M0 Technical Reference Manual, available from the www.arm.com website.
Description 2 STM32F051x4 STM32F051x6 STM32F051x8 Description The STM32F051xx microcontrollers incorporate the high-performance ARM® Cortex®-M0 32-bit RISC core operating at up to 48 MHz frequency, high-speed embedded memories (up to 64 Kbytes of Flash memory and 8 Kbytes of SRAM), and an extensive range of enhanced peripherals and I/Os.
STM32F051x4 STM32F051x6 STM32F051x8 Description Table 2. STM32F051xx family device features and peripheral count Peripheral STM32F051Kx Flash memory (Kbyte) 16 32 64 STM32F051T8 64 STM32F051Cx 16 SRAM (Kbyte) 32 1 (16-bit) General purpose 5 (16-bit) 1 (32-bit) Basic 1 (16-bit) SPI [I2S](1) 1 [1](2) 1 [1](2) 1 [1](2) 2C 1(3) 1(3) 1(3) Comm. interfaces I USART 16 32 1(4) 2 2 2 [1] 2 [1] 1(3) 2 1(4) CEC 2 2 1(4) 2 1 12-bit ADC (number of channels) 1 (10 ext. + 3 int.
Description STM32F051x4 STM32F051x6 STM32F051x8 Figure 1. Block diagram 32:(5 6HULDO :LUH 'HEXJ 2EO )ODVK PHPRU\ LQWHUIDFH 6:&/. 6:',2 DV $) 65$0 FRQWUROOHU 19,& %XV PDWUL[ &257(; 0 &38 I0$; 0+] 9'' )ODVK *3/ XS WR .% ELW # 9'' 65$0 .% # 9''$ +6, +6, 3//&/.
STM32F051x4 STM32F051x6 STM32F051x8 3 Functional overview Functional overview Figure 1 shows the general block diagram of the STM32F051xx devices. 3.1 ARM®-Cortex®-M0 core The ARM® Cortex®-M0 is a generation of ARM 32-bit RISC processors for embedded systems.
Functional overview 3.4 STM32F051x4 STM32F051x6 STM32F051x8 Cyclic redundancy check calculation unit (CRC) The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit data word and a CRC-32 (Ethernet) polynomial. Among other applications, CRC-based techniques are used to verify data transmission or storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of verifying the Flash memory integrity.
STM32F051x4 STM32F051x6 STM32F051x8 Functional overview In Standby mode, it is put in power down mode. In this mode, the regulator output is in high impedance and the kernel circuitry is powered down, inducing zero consumption (but the contents of the registers and SRAM are lost). 3.5.
Functional overview STM32F051x4 STM32F051x6 STM32F051x8 Figure 2. Clock tree )/,7)&/. , & 6: )ODVK PHPRU\ SURJUDPPLQJ LQWHUIDFH +6, , & 6<6&/. , 6 0+] +6, 5& +6, +6, &(&6: /6( &(& +&/. 3//65& 35(',9 6: 3//08/ 26&B,1 0+] +6( 26& 6<6&/. 3// [ [ [ « « +35( 335( &66 [ [ +6( 0+] 5& +6, +6, 26& B287 57&&/. /6( 57& 57&6(/ N+] /6, 5& &.02'( &.02'( 3&/. 7,0 86$57 6: 6<6&/.
STM32F051x4 STM32F051x6 STM32F051x8 Functional overview The I/O configuration can be locked if needed following a specific sequence in order to avoid spurious writing to the I/Os registers. 3.8 Direct memory access controller (DMA) The 5-channel general-purpose DMAs manage memory-to-memory, peripheral-to-memory and memory-to-peripheral transfers. The DMA supports circular buffer management, removing the need for user code intervention when the controller reaches the end of the buffer.
Functional overview STM32F051x4 STM32F051x6 STM32F051x8 sensor, voltage reference, VBAT voltage measurement) channels and performs conversions in single-shot or scan modes. In scan mode, automatic conversion is performed on a selected group of analog inputs. The ADC can be served by the DMA controller. An analog watchdog feature allows very precise monitoring of the converted voltage of one, some or all selected channels.
STM32F051x4 STM32F051x6 STM32F051x8 3.10.3 Functional overview VBAT battery voltage monitoring This embedded hardware feature allows the application to measure the VBAT battery voltage using the internal ADC channel ADC_IN18. As the VBAT voltage may be higher than VDDA, and thus outside the ADC input range, the VBAT pin is internally connected to a bridge divider by 2. As a consequence, the converted digital value is half the VBAT voltage. 3.
Functional overview STM32F051x4 STM32F051x6 STM32F051x8 hardware touch sensing controller and only requires few external components to operate. For operation, one capacitive sensing GPIO in each group is connected to an external capacitor and cannot be used as effective touch sensing channel. The touch sensing controller is fully supported by the STMTouch touch sensing firmware library, which is free to use and allows touch sensing functionality to be implemented reliably in the end application. Table 5.
STM32F051x4 STM32F051x6 STM32F051x8 3.14 Functional overview Timers and watchdogs The STM32F051xx devices include up to six general-purpose timers, one basic timer and an advanced control timer. Table 7 compares the features of the different timers. Table 7.
Functional overview 3.14.2 STM32F051x4 STM32F051x6 STM32F051x8 General-purpose timers (TIM2, 3, 14, 15, 16, 17) There are six synchronizable general-purpose timers embedded in the STM32F051xx devices (see Table 7 for differences). Each general-purpose timer can be used to generate PWM outputs, or as simple time base. TIM2, TIM3 STM32F051xx devices feature two synchronizable 4-channel general-purpose timers. TIM2 is based on a 32-bit auto-reload up/downcounter and a 16-bit prescaler.
STM32F051x4 STM32F051x6 STM32F051x8 Functional overview can be used either as a watchdog to reset the device when a problem occurs, or as a free running timer for application timeout management. It is hardware or software configurable through the option bytes. The counter can be frozen in debug mode. 3.14.5 System window watchdog (WWDG) The system window watchdog is based on a 7-bit downcounter that can be set as free running. It can be used as a watchdog to reset the device when a problem occurs.
Functional overview STM32F051x4 STM32F051x6 STM32F051x8 The RTC clock sources can be: 3.16 • a 32.768 kHz external crystal • a resonator or oscillator • the internal low-power RC oscillator (typical frequency of 40 kHz) • the high-speed external clock divided by 32 Inter-integrated circuit interface (I2C) Up to two I2C interfaces (I2C1 and I2C2) can operate in multimaster or slave modes.
STM32F051x4 STM32F051x6 STM32F051x8 Functional overview Table 9. STM32F051xx I2C implementation (continued) I2C features(1) I2C1 I2C2 SMBus X - Wakeup from STOP X - 1. X = supported. 3.17 Universal synchronous/asynchronous receiver/transmitter (USART) The device embeds up to two universal synchronous/asynchronous receivers/transmitters (USART1, USART2) which communicate at speeds of up to 6 Mbit/s.
Functional overview 3.18 STM32F051x4 STM32F051x6 STM32F051x8 Serial peripheral interface (SPI) / Inter-integrated sound interface (I2S) Up to two SPIs are able to communicate up to 18 Mbit/s in slave and master modes in fullduplex and half-duplex communication modes. The 3-bit prescaler gives 8 master mode frequencies and the frame size is configurable from 4 bits to 16 bits.
STM32F051x4 STM32F051x6 STM32F051x8 4 Pinouts and pin descriptions Pinouts and pin descriptions /4)3 3) 3) 3$ 3$ 3$ 3$ 3$ 3$ 3& 3& 3& 3& 3% 3% 3% 3% 3$ 3) 3) 3$ 3$ 3$ 3$ 3& 3& 3% 3% 3% 3% 3% 966 9'' 9%$7 3& 3& 26& B,1 3& 26&
Pinouts and pin descriptions STM32F051x4 STM32F051x6 STM32F051x8 Figure 4.
STM32F051x4 STM32F051x6 STM32F051x8 Pinouts and pin descriptions Figure 6.
Pinouts and pin descriptions STM32F051x4 STM32F051x6 STM32F051x8 /4)3 3$ 3$ 3$ 3$ 3$ 3$ 3$ 9'' 3$ 3$ 3$ 3$ 3$ 3% 3% 966 9'' 3) 26&B,1 3) 26&B287 1567 9''$ 3$ 3$ 3$ 7RS YLHZ 966 %227 3% 3% 3% 3% 3% 3$ Figure 8. LQFP32 package pinout 06Y 9 Figure 9.
STM32F051x4 STM32F051x6 STM32F051x8 Pinouts and pin descriptions Table 12. Legend/abbreviations used in the pinout table Name Abbreviation Definition Unless otherwise specified in brackets below the pin name, the pin function during and after reset is the same as the actual pin name Pin name Pin type I/O structure S Supply pin I Input only pin I/O Input / output pin FT 5 V tolerant I/O FTf 5 V tolerant I/O, FM+ capable TTa 3.3 V tolerant I/O directly connected to ADC TC Standard 3.
Pinouts and pin descriptions STM32F051x4 STM32F051x6 STM32F051x8 Table 13.
STM32F051x4 STM32F051x6 STM32F051x8 Pinouts and pin descriptions Table 13.
Pinouts and pin descriptions STM32F051x4 STM32F051x6 STM32F051x8 Table 13.
STM32F051x4 STM32F051x6 STM32F051x8 Pinouts and pin descriptions Table 13.
Pinouts and pin descriptions STM32F051x4 STM32F051x6 STM32F051x8 Table 13.
AF0 - EVENTOUT TIM15_CH1 TIM15_CH2 SPI1_NSS, I2S1_WS SPI1_SCK, I2S1_CK SPI1_MISO, I2S1_MCK SPI1_MOSI, I2S1_SD MCO TIM15_BKIN TIM17_BKIN EVENTOUT EVENTOUT SWDIO SWCLK SPI1_NSS, I2S1_WS Pin name PA0 Downloaded from Arrow.com.
/121 Downloaded from Arrow.com.
STM32F051x4 STM32F051x6 STM32F051x8 5 Memory mapping Memory mapping To the difference of STM32F051x8 memory map in Figure 10, the two bottom code memory spaces of STM32F051x4/STM32F051x6 end at 0x0000 3FFF/0x0000 7FFF and 0x0800 3FFF/0x0000 7FFF, respectively. Figure 10.
Memory mapping STM32F051x4 STM32F051x6 STM32F051x8 Table 16. STM32F051xx peripheral register boundary addresses Bus AHB2 AHB1 APB 40/121 Downloaded from Arrow.com.
STM32F051x4 STM32F051x6 STM32F051x8 Memory mapping Table 16.
Electrical characteristics STM32F051x4 STM32F051x6 STM32F051x8 6 Electrical characteristics 6.1 Parameter conditions Unless otherwise specified, all voltages are referenced to VSS. 6.1.
STM32F051x4 STM32F051x6 STM32F051x8 6.1.6 Electrical characteristics Power supply scheme Figure 13. Power supply scheme 9%$7 %DFNXS FLUFXLWU\ /6( 57& %DFNXS UHJLVWHUV ± 9 3RZHU VZLWFK 9'' 9&25( [ 9'' 5HJXODWRU 287 [ Q) *3 , 2V ,1 [ ) /HYHO VKLIWHU 9'',2 ,2 ORJLF .HUQHO ORJLF &38 'LJLWDO 0HPRULHV [ 966 9''$ 9''$ Q) ) 95() 95() $'& '$& $QDORJ 5&V 3// « 966$ 06 9 Caution: Each power supply pair (VDD/VSS, VDDA/VSSA etc.
Electrical characteristics 6.1.7 STM32F051x4 STM32F051x6 STM32F051x8 Current consumption measurement Figure 14. Current consumption measurement scheme , ''B9%$7 9%$7 ,'' 9'' ,''$ 9''$ 06 9 44/121 Downloaded from Arrow.com.
STM32F051x4 STM32F051x6 STM32F051x8 6.2 Electrical characteristics Absolute maximum ratings Stresses above the absolute maximum ratings listed in Table 17: Voltage characteristics, Table 18: Current characteristics and Table 19: Thermal characteristics may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Table 17.
Electrical characteristics STM32F051x4 STM32F051x6 STM32F051x8 Table 18. Current characteristics Symbol Ratings Max.
STM32F051x4 STM32F051x6 STM32F051x8 6.3 Operating conditions 6.3.1 General operating conditions Electrical characteristics Table 20. General operating conditions Symbol Parameter Conditions Min Max fHCLK Internal AHB clock frequency - 0 48 fPCLK Internal APB clock frequency - 0 48 VDD Standard operating voltage - 2.0 3.6 VDD 3.6 2.4 3.6 1.65 3.6 TC and RST I/O –0.3 VDDIOx+0.3 TTa I/O –0.3 VDDA+0.3(1) FT and FTf I/O –0.3 5.5(1) BOOT0 0 5.
Electrical characteristics STM32F051x4 STM32F051x6 STM32F051x8 Table 21. Operating conditions at power-up / power-down Symbol Parameter VDD rise time rate tVDD - VDD fall time rate VDDA rise time rate tVDDA 6.3.
STM32F051x4 STM32F051x6 STM32F051x8 Electrical characteristics Table 23. Programmable voltage detector characteristics (continued) Symbol Parameter Conditions Min Typ Max Unit Rising edge 2.66 2.78 2.9 V Falling edge 2.56 2.68 2.8 V Rising edge 2.76 2.88 3 V Falling edge 2.66 2.78 2.9 V VPVD6 PVD threshold 6 VPVD7 PVD threshold 7 VPVDhyst(1) PVD hysteresis - 100 - mV PVD current consumption - 0.15 0.26(1) µA IDD(PVD) 1.
Electrical characteristics STM32F051x4 STM32F051x6 STM32F051x8 Typical and maximum current consumption The MCU is placed under the following conditions: • All I/O pins are in analog input mode • All peripherals are disabled except when explicitly mentioned • • The Flash memory access time is adjusted to the fHCLK frequency: – 0 wait state and Prefetch OFF from 0 to 24 MHz – 1 wait state and Prefetch ON above 24 MHz When the peripherals are enabled fPCLK = fHCLK The parameters given in Table 25
STM32F051x4 STM32F051x6 STM32F051x8 Electrical characteristics Table 25. Typical and maximum current consumption from VDD at 3.6 V (continued) All peripherals enabled Symbol Parameter Conditions HSE bypass, PLL on IDD Supply current in Sleep mode HSE bypass, PLL off HSI clock, PLL on HSI clock, PLL off fHCLK Max @ TA(1) Typ All peripherals disabled Max @ TA(1) Typ 25 °C 85 °C 105 °C 48 MHz 14.0 15.3(2) 15.3 16.0(2) 32 MHz 9.5 10.2 10.2 24 MHz 7.3 7.8 8 MHz 2.
Electrical characteristics STM32F051x4 STM32F051x6 STM32F051x8 Table 27. Typical and maximum current consumption in Stop and Standby modes Parameter IDD Supply current in Standby mode Supply current in Stop mode IDDA Supply current in Standby mode Supply current in Stop mode Supply current in Standby mode 2.0 V 2.4 V 2.7 V 3.0 V 3.3 V 3.6 V TA = TA = TA = 25 °C 85 °C 105 °C Regulator in run mode, all oscillators OFF 15 15.1 15.3 15.5 15.
STM32F051x4 STM32F051x6 STM32F051x8 Electrical characteristics Table 28. Typical and maximum current consumption from the VBAT supply Max(1) Typ @ VBAT 2.4 V 2.7 V 3.3 V 3.6 V RTC domain IDD_VBAT supply current Conditions 1.8 V Parameter 1.65 V Symbol TA = 25 °C LSE & RTC ON; “Xtal mode”: lower driving capability; LSEDRV[1:0] = '00' 0.5 0.5 0.6 0.7 0.8 0.9 1.0 LSE & RTC ON; “Xtal mode” higher driving capability; LSEDRV[1:0] = '11' 0.8 TA = TA = 85 °C 105 °C 1.3 Unit 1.7 µA 0.
Electrical characteristics STM32F051x4 STM32F051x6 STM32F051x8 Table 29. Typical current consumption, code executing from Flash memory, running from HSE 8 MHz crystal Typical consumption in Run mode Symbol IDD IDDA Parameter Current consumption from VDD supply Current consumption from VDDA supply fHCLK Typical consumption in Sleep mode Unit Peripherals Peripherals Peripherals Peripherals enabled disabled enabled disabled 48 MHz 23.2 13.3 13.2 3.1 36 MHz 17.6 10.3 10.1 2.6 32 MHz 15.
STM32F051x4 STM32F051x6 STM32F051x8 Electrical characteristics trigger circuits used to discriminate the input value. Unless this specific configuration is required by the application, this supply current consumption can be avoided by configuring these I/Os in analog mode. This is notably the case of ADC input pins which should be configured as analog inputs.
Electrical characteristics STM32F051x4 STM32F051x6 STM32F051x8 Table 30. Switching output I/O current consumption Symbol Parameter Conditions(1) VDDIOx = 3.3 V C =CINT VDDIOx = 3.3 V CEXT = 0 pF C = CINT + CEXT+ CS VDDIOx = 3.3 V CEXT = 10 pF C = CINT + CEXT+ CS ISW I/O current consumption VDDIOx = 3.3 V CEXT = 22 pF C = CINT + CEXT+ CS VDDIOx = 3.3 V CEXT = 33 pF C = CINT + CEXT+ CS VDDIOx = 3.3 V CEXT = 47 pF C = CINT + CEXT+ CS C = Cint VDDIOx = 2.4 V CEXT = 47 pF C = CINT + CEXT+ CS C = Cint 1.
STM32F051x4 STM32F051x6 STM32F051x8 Electrical characteristics On-chip peripheral current consumption The current consumption of the on-chip peripherals is given in Table 31.
Electrical characteristics STM32F051x4 STM32F051x6 STM32F051x8 Table 31. Peripheral current consumption (continued) Peripheral APB-Bridge APB Typical consumption at 25 °C (2) Unit 3 SYSCFG 3 ADC(3) 5 TIM1 17 SPI1 10 USART1 19 TIM15 11 TIM16 8 TIM17 8 DBG (MCU Debug Support) 0.5 TIM2 17 TIM3 13 TIM6 3 TIM14 6 WWDG 1 SPI2 7 USART2 7 I2C1 4 I2C2 5 DAC 2 PWR 1 CEC 2 All APB peripherals µA/MHz 149 1.
STM32F051x4 STM32F051x6 STM32F051x8 6.3.6 Electrical characteristics Wakeup time from low-power mode The wakeup times given in Table 32 are the latency between the event and the execution of the first user instruction. The device goes in low-power mode after the WFE (Wait For Event) instruction, in the case of a WFI (Wait For Interruption) instruction, 16 CPU cycles must be added to the following timings due to the interrupt latency in the Cortex M0 architecture.
Electrical characteristics STM32F051x4 STM32F051x6 STM32F051x8 1. Guaranteed by design, not tested in production. Figure 15. High-speed external clock source AC timing diagram WZ +6(+ 9+6(+ 9+6(/ WU +6( WI +6( W WZ +6(/ 7+6( 06 9 Low-speed external user clock generated from an external source In bypass mode the LSE oscillator is switched off and the input pin is a standard GPIO. The external clock signal has to respect the I/O characteristics in Section 6.3.14.
STM32F051x4 STM32F051x6 STM32F051x8 Electrical characteristics High-speed external clock generated from a crystal/ceramic resonator The high-speed external (HSE) clock can be supplied with a 4 to 32 MHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on design simulation results obtained with typical external components specified in Table 35.
Electrical characteristics STM32F051x4 STM32F051x6 STM32F051x8 Figure 17. Typical application with an 8 MHz crystal 5HVRQDWRU ZLWK LQWHJUDWHG FDSDFLWRUV &/ 26&B,1 0+] UHVRQDWRU &/ 5(;7 I+6( 5) %LDV FRQWUROOHG JDLQ 26&B287 06 9 1. REXT value depends on the crystal characteristics. Low-speed external clock generated from a crystal resonator The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal resonator oscillator.
STM32F051x4 STM32F051x6 STM32F051x8 Electrical characteristics Table 36. LSE oscillator characteristics (fLSE = 32.768 kHz) Symbol gm tSU(LSE)(3) Conditions(1) Min(2) Typ LSEDRV[1:0]=00 lower driving capability 5 - - LSEDRV[1:0]= 01 medium low driving capability 8 - - LSEDRV[1:0] = 10 medium high driving capability 15 - - LSEDRV[1:0]=11 higher driving capability 25 - - VDDIOx is stabilized - 2 - Parameter Oscillator transconductance Startup time Max(2) Unit µA/V s 1.
Electrical characteristics STM32F051x4 STM32F051x6 STM32F051x8 High-speed internal (HSI) RC oscillator Table 37. HSI oscillator characteristics(1) Symbol Parameter fHSI Conditions Min Typ - - Frequency TRIM HSI user trimming step DuCy(HSI) Duty cycle Accuracy of the HSI oscillator ACCHSI - - - (2) 45 IDDA(HSI) Unit 8 - MHz - (2) - % 1 (2) 55 % TA = -40 to 105°C (3) -2.8 - 3.8 TA = -10 to 85°C -1.9(3) - 2.3(3) TA = 0 to 85°C -1.9(3) - 2(3) TA = 0 to 70°C -1.
STM32F051x4 STM32F051x6 STM32F051x8 Electrical characteristics High-speed internal 14 MHz (HSI14) RC oscillator (dedicated to ADC) Table 38. HSI14 oscillator characteristics(1) Symbol fHSI14 TRIM Parameter Conditions Min Typ - - 14 Frequency HSI14 user-trimming step DuCy(HSI14) Duty cycle - - - (2) 45 Accuracy of the HSI14 oscillator (factory calibrated) TA = –10 to 85 °C TA = 25 °C tsu(HSI14) IDDA(HSI14) - MHz (2) - % 1 55 (2) % (3) % (3) - 5.1 –3.2(3) - 3.1(3) % –2.
Electrical characteristics STM32F051x4 STM32F051x6 STM32F051x8 Low-speed internal (LSI) RC oscillator Table 39. LSI oscillator characteristics(1) Symbol Parameter fLSI tsu(LSI) Min Typ Max Unit 30 40 50 kHz LSI oscillator startup time - - 85 µs LSI oscillator power consumption - 0.75 1.2 µA Frequency (2) IDDA(LSI)(2) 1. VDDA = 3.3 V, TA = –40 to 105 °C unless otherwise specified. 2. Guaranteed by design, not tested in production. 6.3.
STM32F051x4 STM32F051x6 STM32F051x8 Electrical characteristics Table 42. Flash memory endurance and data retention Symbol NEND Parameter Endurance Conditions TA = –40 to +105 °C 1 tRET Data retention kcycle(2) Min(1) Unit 10 kcycle at TA = 85 °C 30 at TA = 105 °C 10 10 kcycle(2) at TA = 55 °C 20 1 kcycle (2) Year 1. Data based on characterization results, not tested in production. 2. Cycling performed over the whole temperature range. 6.3.
Electrical characteristics STM32F051x4 STM32F051x6 STM32F051x8 Software recommendations The software flowchart must include the management of runaway conditions such as: • Corrupted program counter • Unexpected reset • Critical Data corruption (for example control registers) Prequalification trials Most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1 second.
STM32F051x4 STM32F051x6 STM32F051x8 Electrical characteristics Table 45. ESD absolute maximum ratings Symbol Ratings Conditions Packages Class Maximum value(1) Unit VESD(HBM) Electrostatic discharge voltage TA = +25 °C, conforming (human body model) to JESD22-A114 All 2 2000 V VESD(CDM) Electrostatic discharge voltage TA = +25 °C, conforming (charge device model) to ANSI/ESD STM5.3.1 All C3 250 V 1. Data based on characterization results, not tested in production.
Electrical characteristics STM32F051x4 STM32F051x6 STM32F051x8 Table 47. I/O current injection susceptibility Functional susceptibility Symbol Description Unit Negative Positive injection injection IINJ 6.3.
STM32F051x4 STM32F051x6 STM32F051x8 Electrical characteristics Table 48. I/O static characteristics (continued) Symbol Ilkg RPU Parameter Input leakage current(2) Weak pull-up equivalent resistor (3) RPD Weak pull-down equivalent resistor(3) CIO I/O pin capacitance Conditions Min Typ Max TC, FT and FTf I/O TTa in digital mode VSS ≤ VIN ≤ VDDIOx - - ± 0.1 TTa in digital mode VDDIOx ≤ VIN ≤ VDDA - - 1 TTa in analog mode VSS ≤ VIN ≤ VDDA - - ± 0.
Electrical characteristics STM32F051x4 STM32F051x6 STM32F051x8 Figure 21.
STM32F051x4 STM32F051x6 STM32F051x8 Electrical characteristics Output driving current The GPIOs (general purpose input/outputs) can sink or source up to +/-8 mA, and sink or source up to +/- 20 mA (with a relaxed VOL/VOH). In the user application, the number of I/O pins which can drive current must be limited to respect the absolute maximum rating specified in Section 6.
Electrical characteristics STM32F051x4 STM32F051x6 STM32F051x8 Input/output AC characteristics The definition and values of input/output AC characteristics are given in Figure 23 and Table 50, respectively. Unless otherwise specified, the parameters given are derived from tests performed under the ambient temperature and supply voltage conditions summarized in Table 20: General operating conditions. Table 50.
STM32F051x4 STM32F051x6 STM32F051x8 Electrical characteristics Figure 23. I/O AC characteristics definition W I ,2 RXW W U ,2 RXW 7 0D[LPXP IUHTXHQF\ LV DFKLHYHG LI W W U I 7 DQG LI WKH GXW\ F\FOH LV ZKHQ ORDGHG E\ & - VHH WKH WDEOH , 2 $& FKDUDFWHULVWLFV GHILQLWLRQ 06 9 6.3.15 NRST pin characteristics The NRST pin input driver uses the CMOS technology. It is connected to a permanent pullup resistor, RPU.
Electrical characteristics STM32F051x4 STM32F051x6 STM32F051x8 Figure 24. Recommended NRST pin protection ([WHUQDO UHVHW FLUFXLW 9 '' 1567 5 38 ,QWHUQDO UHVHW )LOWHU ) 06 9 1. The external capacitor protects the device against parasitic resets. 2. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in Table 51: NRST pin characteristics. Otherwise the reset will not be taken into account by the device. 6.3.
STM32F051x4 STM32F051x6 STM32F051x8 Electrical characteristics Table 52. ADC characteristics (continued) Symbol Parameter WLATENCY(2)(4) tlatr (2) ADC_DR register ready latency Conditions Min Typ Max ADC clock = HSI14 1.5 ADC cycles + 2 fPCLK cycles - 1.5 ADC cycles + 3 fPCLK cycles ADC clock = PCLK/2 - 4.5 - fPCLK cycle ADC clock = PCLK/4 - 8.5 - fPCLK cycle fADC = fPCLK/2 = 14 MHz 0.196 µs fADC = fPCLK/2 5.5 1/fPCLK 0.219 µs 10.
Electrical characteristics STM32F051x4 STM32F051x6 STM32F051x8 Table 53. RAIN max for fADC = 14 MHz (continued) Ts (cycles) tS (µs) RAIN max (kΩ)(1) 28.5 2.04 25.2 41.5 2.96 37.2 55.5 3.96 50 71.5 5.11 NA 239.5 17.1 NA 1. Guaranteed by design, not tested in production. Table 54. ADC accuracy(1)(2)(3) Symbol Parameter Test conditions Typ Max(4) ±1.3 ±2 ±1 ±1.5 ±0.5 ±1.5 ±0.
STM32F051x4 STM32F051x6 STM32F051x8 Electrical characteristics Figure 25.
Electrical characteristics 6.3.17 STM32F051x4 STM32F051x6 STM32F051x8 DAC electrical specifications Table 55. DAC characteristics Symbol Parameter Min Typ Max Unit Comments VDDA Analog supply voltage for DAC ON 2.4 - 3.6 V RLOAD(1) Resistive load with buffer ON 5 - - kΩ Load is referred to ground RO(1) CLOAD(1) Impedance output with buffer OFF - - 15 kΩ When the buffer is OFF, the Minimum resistive load between DAC_OUT and VSS to have a 1% accuracy is 1.
STM32F051x4 STM32F051x6 STM32F051x8 Electrical characteristics Table 55.
Electrical characteristics 6.3.18 STM32F051x4 STM32F051x6 STM32F051x8 Comparator characteristics Table 56. Comparator characteristics Symbol Parameter Conditions Min(1) Typ Max(1) Analog supply voltage - VDD - 3.6 VIN Comparator input voltage range - 0 - VDDA VSC VREFINT scaler offset voltage - - ±5 ±10 tS_SC VREFINT scaler startup time from power down First VREFINT scaler activation after device power on - - Next activations - - 0.
STM32F051x4 STM32F051x6 STM32F051x8 Electrical characteristics Table 56.
Electrical characteristics 6.3.19 STM32F051x4 STM32F051x6 STM32F051x8 Temperature sensor characteristics Table 57. TS characteristics Symbol Parameter TL(1) Avg_Slope Min Typ Max Unit - ±1 ±2 °C 4.0 4.3 4.6 mV/°C 1.34 1.43 1.52 V VSENSE linearity with temperature (1) V30 Average slope Voltage at 30 °C (± 5 °C) (2) tSTART(1) ADC_IN16 buffer startup time - - 10 µs tS_temp(1) ADC sampling time when reading the temperature 4 - - µs 1.
STM32F051x4 STM32F051x6 STM32F051x8 Electrical characteristics Table 60. IWDG min/max timeout period at 40 kHz (LSI)(1) Prescaler divider PR[2:0] bits Min timeout RL[11:0]= 0x000 Max timeout RL[11:0]= 0xFFF /4 0 0.1 409.6 /8 1 0.2 819.2 /16 2 0.4 1638.4 /32 3 0.8 3276.8 /64 4 1.6 6553.6 /128 5 3.2 13107.2 /256 6 or 7 6.4 26214.4 Unit ms 1. These timings are given for a 40 kHz clock but the microcontroller internal RC frequency can vary from 30 to 60 kHz.
Electrical characteristics STM32F051x4 STM32F051x6 STM32F051x8 Table 62. I2C analog filter characteristics(1) Symbol tAF Parameter Maximum width of spikes that are suppressed by the analog filter Min Max Unit 50(2) 260(3) ns 1. Guaranteed by design, not tested in production. 2. Spikes with widths below tAF(min) are filtered. 3.
STM32F051x4 STM32F051x6 STM32F051x8 Electrical characteristics Figure 29. SPI timing diagram - slave mode and CPHA = 0 166 LQSXW 6&. ,QSXW W68 166 &3+$ &32/ &3+$ &32/ WK 166 WF 6&. WZ 6&.+ WZ 6&./ W9 62 WD 62 0,62 287387 WU 6&. WI 6&. WK 62 06% 287 %,7 287 06% ,1 %,7 ,1 WGLV 62 /6% 287 WVX 6, 026, ,1387 /6% ,1 WK 6, DL F Figure 30. SPI timing diagram - slave mode and CPHA = 1 166 LQSXW 6&. LQSXW W68 166 &3+$ &32/ &3+$ &32/ WZ 6&.+ WZ 6&.
Electrical characteristics STM32F051x4 STM32F051x6 STM32F051x8 Figure 31. SPI timing diagram - master mode +LJK 166 LQSXW 6&. 2XWSXW &3+$ &32/ 6&. 2XWSXW WF 6&. &3+$ &32/ &3+$ &32/ &3+$ &32/ WZ 6&.+ WZ 6&./ WVX 0, 0,62 ,13 87 WU 6&. WI 6&. %,7 ,1 06% ,1 /6% ,1 WK 0, 026, 287387 % , 7 287 06% 287 WY 02 /6% 287 WK 02 DL F 1. Measurement points are done at CMOS levels: 0.3 VDD and 0.7 VDD. Table 64.
STM32F051x4 STM32F051x6 STM32F051x8 Electrical characteristics Table 64. I2S characteristics(1) (continued) Symbol tsu(SD_MR) tsu(SD_SR) th(SD_MR) th(SD_SR) Parameter Data input setup time (2) (2) tv(SD_MT)(2) tv(SD_ST)(2) th(SD_MT) th(SD_ST) Data input hold time Data output valid time Data output hold time Conditions Min Max Master receiver 6 - Slave receiver 2 - Master receiver 4 - Slave receiver 0.
Electrical characteristics STM32F051x4 STM32F051x6 STM32F051x8 Figure 33. I2S master timing diagram (Philips protocol) WI &. WU &. &. RXWSXW WF &. &32/ WZ &.+ &32/ WY :6 WK :6 WZ &./ :6 RXWSXW WY 6'B07 6'WUDQVPLW /6% WUDQVPLW 06% WUDQVPLW /6% UHFHLYH /6% WUDQVPLW WK 6'B05 WVX 6'B05 6'UHFHLYH %LWQ WUDQVPLW WK 6'B07 06% UHFHLYH %LWQ UHFHLYH /6% UHFHLYH 06Y 9 1. Data based on characterization results, not tested in production. 2.
STM32F051x4 STM32F051x6 STM32F051x8 7 Package information Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. 7.1 UFBGA64 package information UFBGA64 is a 64-ball, 5 x 5 mm, 0.5 mm pitch ultra-fine-profile ball grid array package. Figure 34.
Package information STM32F051x4 STM32F051x6 STM32F051x8 Table 65. UFBGA64 package mechanical data (continued) inches(1) millimeters Symbol Min Typ Max Min Typ Max A 0.460 0.530 0.600 0.0181 0.0209 0.0236 b 0.170 0.280 0.330 0.0067 0.0110 0.0130 D 4.850 5.000 5.150 0.1909 0.1969 0.2028 D1 3.450 3.500 3.550 0.1358 0.1378 0.1398 E 4.850 5.000 5.150 0.1909 0.1969 0.2028 E1 3.450 3.500 3.550 0.1358 0.1378 0.1398 e - 0.500 - - 0.0197 - F 0.700 0.750 0.
STM32F051x4 STM32F051x6 STM32F051x8 Package information Figure 36. UFBGA64 package marking example 3URGXFW LGHQWLILFDWLRQ ' 3 ) 'DWH FRGH : 88 6WDQGDUG 67 ORJR 5HYLVLRQ FRGH 3 %DOO LGHQWLILHU 06 9 1. Parts marked as "ES", "E" or accompanied by an Engineering Sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at ST charge.
Package information 7.2 STM32F051x4 STM32F051x6 STM32F051x8 LQFP64 package information LQFP64 is a 64-pin, 10 x 10 mm low-profile quad flat package. Figure 37. LQFP64 package outline PP *$8*( 3/$1( F $ $ $ 6($7,1* 3/$1( & $ FFF & ' ' ' . / / ( ( ( E 3,1 ,'(17,),&$7,21 H :B0(B9 1. Drawing is not to scale. Table 67. LQFP64 package mechanical data inches(1) millimeters Symbol 94/121 Downloaded from Arrow.com.
STM32F051x4 STM32F051x6 STM32F051x8 Package information Table 67. LQFP64 package mechanical data (continued) inches(1) millimeters Symbol Min Typ Max Min Typ Max E3 - 7.500 - - 0.2953 - e - 0.500 - - 0.0197 - K 0° 3.5° 7° 0° 3.5° 7° L 0.450 0.600 0.750 0.0177 0.0236 0.0295 L1 - 1.000 - - 0.0394 - ccc - - 0.080 - - 0.0031 1. Values in inches are converted from mm and rounded to 4 decimal digits. Figure 38.
Package information STM32F051x4 STM32F051x6 STM32F051x8 Device marking The following figure gives an example of topside marking orientation versus pin 1 identifier location. Figure 39. LQFP64 package marking example 5HYLVLRQ FRGH 5 3URGXFW LGHQWLILFDWLRQ 670 ) 5 7 'DWH FRGH z tt 3LQ LGHQWLILHU 06Y 9 1.
STM32F051x4 STM32F051x6 STM32F051x8 7.3 Package information LQFP48 package information LQFP48 is a 48-pin, 7 x 7 mm low-profile quad flat package. Figure 40. LQFP48 package outline C ! ! ! 3%!4).' 0,!.% # MM '!5'% 0,!.% CCC # + ! $ $ , , $ 0). )$%.4)&)#!4)/. % % % B E "?-%?6 1. Drawing is not to scale. DocID022265 Rev 6 97/121 115 Downloaded from Arrow.com.
Package information STM32F051x4 STM32F051x6 STM32F051x8 Table 68. LQFP48 package mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A - - 1.600 - - 0.0630 A1 0.050 - 0.150 0.0020 - 0.0059 A2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 - 0.200 0.0035 - 0.0079 D 8.800 9.000 9.200 0.3465 0.3543 0.3622 D1 6.800 7.000 7.200 0.2677 0.2756 0.2835 D3 - 5.500 - - 0.2165 - E 8.800 9.000 9.
STM32F051x4 STM32F051x6 STM32F051x8 Package information Device marking The following figure gives an example of topside marking orientation versus pin 1 identifier location. Figure 42. LQFP48 package marking example 3URGXFW LGHQWLILFDWLRQ 670 ) & 7 'DWH FRGH 3LQ LGHQWLILHU < :: 5HYLVLRQ FRGH 5 06Y 9 1.
Package information 7.4 STM32F051x4 STM32F051x6 STM32F051x8 UFQFPN48 package information UFQFPN48 is a 48-lead, 7x7 mm, 0.5 mm pitch, ultra-thin fine-pitch quad flat package. Figure 43. UFQFPN48 package outline 3LQ LGHQWLILHU ODVHU PDUNLQJ DUHD ' $ ( ( 7 GGG $ 6HDWLQJ SODQH E H 'HWDLO < ' ([SRVHG SDG DUHD < ' / & [ SLQ FRUQHU ( 5 W\S 'HWDLO = = $ % B0(B9 1. Drawing is not to scale. 2.
STM32F051x4 STM32F051x6 STM32F051x8 Package information Table 69. UFQFPN48 package mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A 0.500 0.550 0.600 0.0197 0.0217 0.0236 A1 0.000 0.020 0.050 0.0000 0.0008 0.0020 D 6.900 7.000 7.100 0.2717 0.2756 0.2795 E 6.900 7.000 7.100 0.2717 0.2756 0.2795 D2 5.500 5.600 5.700 0.2165 0.2205 0.2244 E2 5.500 5.600 5.700 0.2165 0.2205 0.2244 L 0.300 0.400 0.500 0.0118 0.0157 0.0197 T - 0.
Package information STM32F051x4 STM32F051x6 STM32F051x8 Device marking The following figure gives an example of topside marking orientation versus pin 1 identifier location. Figure 45. UFQFPN48 package marking example 3URGXFW LGHQWLILFDWLRQ 670 ) & 8 'DWH FRGH 3LQ LGHQWLILHU < :: 5HYLVLRQ FRGH 5 06Y 9 1.
STM32F051x4 STM32F051x6 STM32F051x8 7.5 Package information WLCSP36 package information WLCSP36 is a 36-ball, 2.605 x 2.703 mm, 0.4 mm pitch wafer-level chip-scale package. Figure 46. WLCSP36 package outline H EEE = $ EDOO ORFDWLRQ ) H * $ 'HWDLO $ H H ) $ $ $ %XPS VLGH 6LGH YLHZ ; < $ %XPS $ RULHQWDWLRQ UHIHUHQFH HHH = DDD = $ E EDOOV FFF = ; < GGG = :DIHU EDFN VLGH E = 6HDWLQJ SODQH 'HWDLO $ URWDWHG Ϭ>ͺD ͺsϮ 1. Drawing is not to scale. Table 70.
Package information STM32F051x4 STM32F051x6 STM32F051x8 Table 70. WLCSP36 package mechanical data (continued) inches(1) millimeters Symbol Min Typ Max Min Typ Max F - 0.3025 - - 0.0119 - G - 0.3515 - - 0.0138 - aaa - - 0.100 - - 0.0039 bbb - - 0.100 - - 0.0039 ccc - - 0.100 - - 0.0039 ddd - - 0.050 - - 0.0020 eee - - 0.050 - - 0.0020 1. Values in inches are converted from mm and rounded to 4 decimal digits. 2. Back side coating. 3.
STM32F051x4 STM32F051x6 STM32F051x8 Package information Device marking The following figure gives an example of topside marking orientation versus ball A1 identifier location. Figure 48. WLCSP36 package marking example 'RW 3URGXFW LGHQWLILFDWLRQ ' 5HYLVLRQ FRGH 3 'DWH FRGH : 88 06 9 1.
Package information 7.6 STM32F051x4 STM32F051x6 STM32F051x8 LQFP32 package information LQFP32 is a 32-pin, 7 x 7 mm low-profile quad flat package. Figure 49. LQFP32 package outline C ! ! ! 3%!4).' 0,!.% # MM CCC '!5'% 0,!.% # + $ , ! $ , $ 0). )$%.4)&)#!4)/. 1. Drawing is not to scale. Downloaded from Arrow.com. % E 106/121 % % B DocID022265 Rev 6 7@.
STM32F051x4 STM32F051x6 STM32F051x8 Package information Table 72. LQFP32 package mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A - - 1.600 - - 0.0630 A1 0.050 - 0.150 0.0020 - 0.0059 A2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.300 0.370 0.450 0.0118 0.0146 0.0177 c 0.090 - 0.200 0.0035 - 0.0079 D 8.800 9.000 9.200 0.3465 0.3543 0.3622 D1 6.800 7.000 7.200 0.2677 0.2756 0.2835 D3 - 5.600 - - 0.2205 - E 8.800 9.000 9.
Package information STM32F051x4 STM32F051x6 STM32F051x8 Device marking The following figure gives an example of topside marking orientation versus pin 1 identifier location. Figure 51. LQFP32 package marking example 3URGXFW LGHQWLILFDWLRQ 670 ) . 7 'DWH FRGH 3LQ LGHQWLILFDWLRQ < :: 5HYLVLRQ FRGH 5 06Y 9 1.
STM32F051x4 STM32F051x6 STM32F051x8 Package information Figure 52. UFQFPN32 package outline ' $ H $ $ ' GGG & & 6($7,1* 3/$1( E H ( E ( ( / 3,1 ,GHQWLILHU ' / ! " ?-%?6 1. Drawing is not to scale. 2. All leads/pads should also be soldered to the PCB to improve the lead/pad solder joint life. 3. There is an exposed die pad on the underside of the UFQFPN package. This pad is used for the device ground and must be connected. It is referred to as pin 0 in Table: Pin definitions.
Package information STM32F051x4 STM32F051x6 STM32F051x8 Table 73. UFQFPN32 package mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A 0.500 0.550 0.600 0.0197 0.0217 0.0236 A1 0.000 0.020 0.050 0.0000 0.0008 0.0020 A3 - 0.152 - - 0.0060 - b 0.180 0.230 0.280 0.0071 0.0091 0.0110 D 4.900 5.000 5.100 0.1929 0.1969 0.2008 D1 3.400 3.500 3.600 0.1339 0.1378 0.1417 D2 3.400 3.500 3.600 0.1339 0.1378 0.1417 E 4.900 5.000 5.100 0.
STM32F051x4 STM32F051x6 STM32F051x8 Package information Device marking The following figure gives an example of topside marking orientation versus pin 1 identifier location. Figure 54. UFQFPN32 package marking example 3URGXFW LGHQWLILFDWLRQ ) . 'DWH FRGH < :: 5HYLVLRQ FRGH 5 'RW SLQ 06Y 9 1.
Package information 7.8 STM32F051x4 STM32F051x6 STM32F051x8 Thermal characteristics The maximum chip junction temperature (TJmax) must never exceed the values given in Table 20: General operating conditions.
STM32F051x4 STM32F051x6 STM32F051x8 Package information Each temperature range suffix corresponds to a specific guaranteed ambient temperature at maximum dissipation and, to a specific maximum junction temperature. As applications do not commonly use the STM32F051xx at maximum dissipation, it is useful to calculate the exact power consumption and junction temperature to determine which temperature range will be best suited to the application.
Package information STM32F051x4 STM32F051x6 STM32F051x8 Using the values obtained in Table 74 TJmax is calculated as follows: – For LQFP64, 45 °C/W TJmax = 100 °C + (45 °C/W × 134 mW) = 100 °C + 6.03 °C = 106.03 °C This is above the range of the suffix 6 version parts (–40 < TJ < 105 °C). In this case, parts must be ordered at least with the temperature range suffix 7 (see Section 8: Part numbering) unless we reduce the power dissipation in order to be able to use suffix 6 parts.
STM32F051x4 STM32F051x6 STM32F051x8 8 Part numbering Part numbering For a list of available options (memory, package, and so on) or for further information on any aspect of this device, please contact your nearest ST sales office. Table 75.
Revision history 9 STM32F051x4 STM32F051x6 STM32F051x8 Revision history Table 76. Document revision history Date Revision 05-Apr-2012 1 Initial release 2 Updated Table: STM32F051xx family device features and peripheral counts for SPI and I2C in 32-pin package. Corrected Group 3 pin order in Table: Capacitive sensing GPIOs available on STM32F051xx devices. Updated the current consumption values in Section: Electrical characteristics.
STM32F051x4 STM32F051x6 STM32F051x8 Revision history Table 76. Document revision history (continued) Date 13-Jan-2014 Revision Changes 4 Modified datasheet title. Added packages UFQFPN48 and UFBGA64. Replaced “backup domain with “RTC domain” throughout the document. Changed SRAM value from “4 to 8 Kbyte” to “8 Kbyte” Replaced IWWDG with IWDG in Figure: Block diagram. Added inputs LSI and LSE to the multiplexer in Figure: Clock tree.
Revision history STM32F051x4 STM32F051x6 STM32F051x8 Table 76. Document revision history (continued) Date 13-Jan-2014 118/121 Downloaded from Arrow.com. Revision Changes 4 (continued) Added “Negative induced leakage current is caused by negative injection and positive induced leakage current is caused by positive injection” in Section Functional susceptibility to I/O current injection. Replaced reference "JESD22-C101" with "ANSI/ESD STM5.3.1" in Table : ESD absolute maximum ratings.
STM32F051x4 STM32F051x6 STM32F051x8 Revision history Table 76. Document revision history (continued) Date 28-Aug-2015 Revision 5 Changes Updated the following: – DAC and power management feature descriptions in Features – Table 2: STM32F051xx family device features and peripheral count – Section 3.5.
Revision history STM32F051x4 STM32F051x6 STM32F051x8 Table 76. Document revision history (continued) Date 28-Aug-2015 16-Dec-2015 120/121 Downloaded from Arrow.com. Revision Changes 5 (continued) – Table 31: Peripheral current consumption Addition of WLCSP36 package.
STM32F051x4 STM32F051x6 STM32F051x8 IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement.