Datasheet

ManualsBrandsST ManualsEmbedded Processors & ControllersMicrocontroller 32bit 256KB UFQFPN

This is information on a product in full production.

June 2017 DocID028798 Rev 3 1/155

STM32L432KB STM32L432KC

Ultra-low-power ARM

Cortex

-M4 32-bit MCU+FPU, 100DMIPS,

up to 256KB Flash, 64KB SRAM, USB FS, analog, audio

Datasheet - production data

Features

• Ultra-low-power with FlexPowerControl

– 1.71 V to 3.6 V power supply

– -40 °C to 85/105/125 °C temperature range

– 8 nA Shutdown mode (2 wakeup pins)

– 28 nA Standby mode (2 wakeup pins)

– 280 nA Standby mode with RTC

– 1.0 µA Stop 2 mode, 1.28 µA with RTC

– 84 µA/MHz run mode

– Batch acquisition mode (BAM)

– 4 µs wakeup from Stop mode

– Brown out reset (BOR)

– Interconnect matrix

• Core: ARM

32-bit Cortex

-M4 CPU with FPU,

Adaptive real-time accelerator (ART

Accelerator™) allowing 0-wait-state execution

from Flash memory, frequency up to 80 MHz,

MPU, 100DMIPS and DSP instructions

• Performance benchmark

– 1.25 DMIPS/MHz (Drystone 2.1)

– 273.55 CoreMark

(3.42 CoreMark/MHz @

80 MHz)

• Energy benchmark

– 176.7 ULPBench

score

• Clock Sources

– 32 kHz crystal oscillator for RTC (LSE)

– Internal 16 MHz factory-trimmed RC (±1%)

– Internal low-power 32 kHz RC (±5%)

– Internal multispeed 100 kHz to 48 MHz

oscillator, auto-trimmed by LSE (better than

±0.25 % accuracy)

– Internal 48 MHz with clock recovery

– 2 PLLs for system clock, USB, audio, ADC

• Up to 26 fast I/Os, most 5 V-tolerant

• RTC with HW calendar, alarms and calibration

• Up to 3 capacitive sensing channels

• 11x timers: 1x 16-bit advanced motor-control,

1x 32-bit and 2x 16-bit general purpose, 2x 16-

bit basic, 2x low-power 16-bit timers (available

in Stop mode), 2x watchdogs, SysTick timer

• Memories

– Up to 256 KB single bank Flash,

proprietary code readout protection

– 64 KB of SRAM including 16 KB with

hardware parity check

– Quad SPI memory interface

• Rich analog peripherals (independent supply)

– 1× 12-bit ADC 5 Msps, up to 16-bit with

hardware oversampling, 200 µA/Msps

– 2x 12-bit DAC, low-power sample and hold

– 1x operational amplifier with built-in PGA

– 2x ultra-low-power comparators

• 14x communication interfaces

– USB 2.0 full-speed crystal less solution

with LPM and BCD

– 1x SAI (serial audio interface)

–2x I2C FM+(1 Mbit/s), SMBus/PMBus

– 3x USARTs (ISO 7816, LIN, IrDA, modem)

– 1x LPUART (Stop2 wake-up)

– 2x SPIs (3x SPIs with the Quad SPI)

– CAN (2.0B Active)

– SWPMI single wire protocol master I/F

– IRTIM (Infrared interface)

• 14-channel DMA controller

• True random number generator

• CRC calculation unit, 96-bit unique ID

UFQFPN32 (5x5)

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Summary of content (155 pages)

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STM32L432KB STM32L432KC Ultra-low-power ARM® Cortex®-M4 32-bit MCU+FPU, 100DMIPS, up to 256KB Flash, 64KB SRAM, USB FS, analog, audio Datasheet - production data Features • Ultra-low-power with FlexPowerControl – 1.71 V to 3.6 V power supply – -40 °C to 85/105/125 °C temperature range – 8 nA Shutdown mode (2 wakeup pins) – 28 nA Standby mode (2 wakeup pins) – 280 nA Standby mode with RTC – 1.0 µA Stop 2 mode, 1.
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STM32L432KB STM32L432KC • Development support: serial wire debug (SWD), JTAG, Embedded Trace Macrocell™ 2/155 Downloaded from Arrow.com.
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STM32L432KB STM32L432KC Contents Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3 Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.1 ARM® Cortex®-M4 core with FPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.
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Contents STM32L432KB STM32L432KC 3.19 Touch sensing controller (TSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 3.20 Random number generator (RNG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 3.21 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 3.21.1 Advanced-control timer (TIM1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 3.21.2 General-purpose timers (TIM2, TIM15, TIM16) . . . .
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STM32L432KB STM32L432KC 7 6.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 6.1.6 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 6.1.7 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 6.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 6.3 Operating conditions . . . . . . . . . . . . . . . . . .
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Contents 9 6/155 Downloaded from Arrow.com. STM32L432KB STM32L432KC Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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STM32L432KB STM32L432KC List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42.
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List of tables Table 43. Table 44. Table 45. Table 46. Table 47. Table 48. Table 49. Table 50. Table 51. Table 52. Table 53. Table 54. Table 55. Table 56. Table 57. Table 58. Table 59. Table 60. Table 61. Table 62. Table 63. Table 64. Table 65. Table 66. Table 67. Table 68. Table 69. Table 70. Table 71. Table 72. Table 73. Table 74. Table 75. Table 76. Table 77. Table 78. Table 79. Table 80. Table 81. Table 82. Table 83. Table 84. Table 85. Table 86. 8/155 Downloaded from Arrow.com.
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STM32L432KB STM32L432KC List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. STM32L432xx block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Introduction 1 STM32L432KB STM32L432KC Introduction This datasheet provides the ordering information and mechanical device characteristics of the STM32L432xx microcontrollers. This document should be read in conjunction with the STM32L43xxx/44xxx/45xxx/46xxx reference manual (RM0394). The reference manual is available from the STMicroelectronics website www.st.com. For information on the ARM® Cortex®-M4 core, please refer to the Cortex®-M4 Technical Reference Manual, available from the www.arm.
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STM32L432KB STM32L432KC 2 Description Description The STM32L432xx devices are the ultra-low-power microcontrollers based on the highperformance ARM® Cortex®-M4 32-bit RISC core operating at a frequency of up to 80 MHz. The Cortex-M4 core features a Floating point unit (FPU) single precision which supports all ARM single-precision data-processing instructions and data types. It also implements a full set of DSP instructions and a memory protection unit (MPU) which enhances application security.
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Description STM32L432KB STM32L432KC Table 1. STM32L432Kx family device features and peripheral counts (continued) Peripheral Timers Comm.
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STM32L432KB STM32L432KC Description Figure 1. STM32L432xx block diagram 1-7567 -7', -7&. 6:&/. ' > @ &/. &6 4XDG 63, PHPRU\ LQWHUIDFH -7$* 6: 038 (70 19,& -7'2 6:' -7'2 75$&(&/. ' %86 75$&('> @ $50 &RUWH[ 0 0+] )38 , %86 $57 $&&(/ &$&+( 51* )ODVK XS WR .% $+% EXV PDWUL[ 6 %86 65$0 .% 65$0 .
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Functional overview STM32L432KB STM32L432KC 3 Functional overview 3.1 ARM® Cortex®-M4 core with FPU The ARM® Cortex®-M4 with FPU processor is the latest generation of ARM processors for embedded systems. It was developed to provide a low-cost platform that meets the needs of MCU implementation, with a reduced pin count and low-power consumption, while delivering outstanding computational performance and an advanced response to interrupts.
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STM32L432KB STM32L432KC 3.4 Functional overview Embedded Flash memory STM32L432xx devices feature up to 256 Kbyte of embedded Flash memory available for storing programs and data in single bank architecture. The Flash memory contains 128 pages of 2 Kbyte. Flexible protections can be configured thanks to option bytes: • Readout protection (RDP) to protect the whole memory.
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Functional overview STM32L432KB STM32L432KC The whole non-volatile memory embeds the error correction code (ECC) feature supporting: 3.5 • single error detection and correction • double error detection. • The address of the ECC fail can be read in the ECC register Embedded SRAM STM32L432xx devices feature 64 Kbyte of embedded SRAM. This SRAM is split into two blocks: • 48 Kbyte mapped at address 0x2000 0000 (SRAM1) • 16 Kbyte located at address 0x1000 0000 with hardware parity check (SRAM2).
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STM32L432KB STM32L432KC 3.7 Functional overview Boot modes At startup, BOOT0 pin or nSWBOOT0 option bit, and BOOT1 option bit are used to select one of three boot options: • Boot from user Flash • Boot from system memory • Boot from embedded SRAM BOOT0 value may come from the PH3-BOOT0 pin or from an option bit depending on the value of a user option bit to free the GPIO pad if needed.
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Functional overview STM32L432KB STM32L432KC Figure 2. Power supply overview 9''$ GRPDLQ 9''$ 966$ $ ' FRQYHUWHUV &RPSDUDWRUV ' $ FRQYHUWHUV 2SHUDWLRQDO DPSOLILHUV 9ROWDJH UHIHUHQFH EXIIHU 9''86% 966 86% WUDQVFHLYHUV 9'' GRPDLQ 9'' 9'',2 , 2 ULQJ 5HVHW EORFN 7HPS VHQVRU 3// +6, 06, +6, 966 6WDQGE\ FLUFXLWU\ :DNHXS ORJLF ,:'* 9ROWDJH UHJXODWRU 9&25( 9&25( GRPDLQ &RUH 0HPRULHV 'LJLWDO SHULSKHUDOV /RZ YROWDJH GHWHFWRU %DFNXS GRPDLQ 9%$7 /6( FU\VWDO . RVF %.
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STM32L432KB STM32L432KC 3.9.3 Functional overview Voltage regulator Two embedded linear voltage regulators supply most of the digital circuitries: the main regulator (MR) and the low-power regulator (LPR). • The MR is used in the Run and Sleep modes and in the Stop 0 mode. • The LPR is used in Low-Power Run, Low-Power Sleep, Stop 1 and Stop 2 modes. It is also used to supply the 16 Kbyte SRAM2 in Standby with SRAM2 retention.
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/155 Downloaded from Arrow.com. Stop 0 LPSleep Sleep LPRun Run Mode DocID028798 Rev 3 MR Range 2 MR Range 1 LPR MR range2 MR range 1 LPR MR range2 MR range 1 Regulator(1) No No No Yes Yes CPU ON ON(5) ON(4) OFF ON(5) ON ON(4) ON(4) ON ON(4) LSE LSI Any except PLL Any Any except PLL Any Flash SRAM Clocks BOR, PVD, PVM RTC, IWDG COMPx (x=1,2) DACx (x=1,2) OPAMPx (x=1) USARTx (x=1,2)(6) LPUART1(6) I2Cx (x=1,3)(7) LPTIMx (x=1,2) *** All other peripherals are frozen.
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Downloaded from Arrow.com. LPR LPR Stop 1 Stop 2 Regulator Mode (1) No No CPU Off Off ON ON LSE LSI LSE LSI Flash SRAM Clocks Reset pin, all I/Os BOR, PVD, PVM RTC, IWDG COMPx (x=1..2) I2C3(7) LPUART1(6) LPTIM1 Reset pin, all I/Os BOR, PVD, PVM RTC, IWDG COMPx (x=1..
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/155 Downloaded from Arrow.com. OFF OFF LPR Regulator Power ed Off Power ed Off CPU Reset pin 5 I/Os (WKUPx)(10) RTC RTC *** All other peripherals are powered off. *** I/O configuration can be floating, pull-up or pulldown(11) Off Power ed Off Power ed Off Reset pin 5 I/Os (WKUPx)(10) BOR, RTC, IWDG LSE LSE LSI BOR, RTC, IWDG *** All other peripherals are powered off.
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STM32L432KB STM32L432KC Functional overview By default, the microcontroller is in Run mode after a system or a power Reset. It is up to the user to select one of the low-power modes described below: • Sleep mode In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can wake up the CPU when an interrupt/event occurs. • Low-power run mode This mode is achieved with VCORE supplied by the low-power regulator to minimize the regulator's operating current.
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Functional overview • STM32L432KB STM32L432KC Shutdown mode The Shutdown mode allows to achieve the lowest power consumption. The internal regulator is switched off so that the VCORE domain is powered off. The PLL, the HSI16, the MSI and the LSI oscillators are also switched off. The RTC can remain active (Shutdown mode with RTC, Shutdown mode without RTC). The BOR is not available in Shutdown mode.
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STM32L432KB STM32L432KC Functional overview Table 4.
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Functional overview STM32L432KB STM32L432KC Table 4. Functionalities depending on the working mode(1) (continued) 26/155 Downloaded from Arrow.com.
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STM32L432KB STM32L432KC Functional overview 1. Legend: Y = Yes (Enable). O = Optional (Disable by default. Can be enabled by software). - = Not available. 2. The Flash can be configured in power-down mode. By default, it is not in power-down mode. 3. The SRAM clock can be gated on or off. 4. SRAM2 content is preserved when the bit RRS is set in PWR_CR3 register. 5. Some peripherals with wakeup from Stop capability can request HSI16 to be enabled.
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Functional overview STM32L432KB STM32L432KC Run Sleep Low-power run Low-power sleep Stop 0 / Stop 1 Stop 2 Table 5.
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STM32L432KB STM32L432KC 3.11 Functional overview Clocks and startup The clock controller (see Figure 3) distributes the clocks coming from different oscillators to the core and the peripherals. It also manages clock gating for low-power modes and ensures clock robustness.
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Functional overview STM32L432KB STM32L432KC Several prescalers allow to configure the AHB frequency, the high speed APB (APB2) and the low speed APB (APB1) domains. The maximum frequency of the AHB and the APB domains is 80 MHz. 30/155 Downloaded from Arrow.com.
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STM32L432KB STM32L432KC Functional overview Figure 3. Clock tree WR ,:'* >^/ Z ϯϮ Ŭ,ǌ /6&2 WR 57& 26& B287 >^ K^ ϯϮ͘ϳϲϴ Ŭ,ǌ ͬϯϮ 26& B,1 /6( /6, +6( 0&2 ĺ㻝㻢 WR 3:5 6<6&/. +6, &.B,1 WR $+% EXV FRUH PHPRU\ DQG '0$ ůŽĐŬ ƐŽƵƌĐĞ ĐŽŶƚƌŽů +6, , WZ ^ ͬ ϭ͕Ϯ͕͘͘ϱϭϮ +6( ůŽĐŬ ĚĞƚĞĐƚŽƌ +&/. )&/. &RUWH[ IUHH UXQQLQJ FORFN WR &RUWH[ V\VWHP WLPHU ͬ ϴ 06, +6, 6<6&/. W ϭ WZ ^ ͬ ϭ͕Ϯ͕ϰ͕ϴ͕ϭϲ 3&/. WR $3% SHULSKHUDOV ǆϭ Žƌ ǆϮ ,^/ Z ϭϲ D,ǌ /6( +6, 6<6&/.
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Functional overview 3.12 STM32L432KB STM32L432KC General-purpose inputs/outputs (GPIOs) Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the GPIO pins are shared with digital or analog alternate functions. Fast I/O toggling can be achieved thanks to their mapping on the AHB2 bus.
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STM32L432KB STM32L432KC Functional overview 3.14 Interrupts and events 3.14.1 Nested vectored interrupt controller (NVIC) The devices embed a nested vectored interrupt controller able to manage 16 priority levels, and handle up to 61 maskable interrupt channels plus the 16 interrupt lines of the Cortex®M4.
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Functional overview 3.15 STM32L432KB STM32L432KC Analog to digital converter (ADC) The device embeds a successive approximation analog-to-digital converter with the following features: • 12-bit native resolution, with built-in calibration • 5.33 Msps maximum conversion rate with full resolution Down to 18.75 ns sampling time – Increased conversion rate for lower resolution (up to 8.88 Msps for 6-bit resolution) • Up to 10 external channels.
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STM32L432KB STM32L432KC Functional overview Table 7. Temperature sensor calibration values 3.15.2 Calibration value name Description Memory address TS_CAL1 TS ADC raw data acquired at a temperature of 30 °C (± 5 °C), VDDA = VREF+ = 3.0 V (± 10 mV) 0x1FFF 75A8 - 0x1FFF 75A9 TS_CAL2 TS ADC raw data acquired at a temperature of 130 °C (± 5 °C), VDDA = VREF+ = 3.
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Functional overview 3.17 STM32L432KB STM32L432KC Comparators (COMP) The STM32L432xx devices embed two rail-to-rail comparators with programmable reference voltage (internal or external), hysteresis and speed (low speed for low-power) and with selectable output polarity. The reference voltage can be one of the following: • External I/O • DAC output channels • Internal reference voltage or submultiple (1/4, 1/2, 3/4).
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STM32L432KB STM32L432KC Functional overview The main features of the touch sensing controller are the following: • Proven and robust surface charge transfer acquisition principle • Supports up to 3 capacitive sensing channels • Up to 3 capacitive sensing channels can be acquired in parallel offering a very good response time • Spread spectrum feature to improve system robustness in noisy environments • Full hardware management of the charge transfer acquisition sequence • Programmable charge tr
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Functional overview STM32L432KB STM32L432KC Table 9. Timer feature comparison (continued) Timer type Timer Counter resolution Counter type Prescaler factor DMA request generation Capture/ compare channels Complementary outputs Generalpurpose TIM16 16-bit Up Any integer between 1 and 65536 Yes 1 1 Basic TIM6, TIM7 16-bit Up Any integer between 1 and 65536 Yes 0 No 3.21.
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STM32L432KB STM32L432KC 3.21.2 Functional overview General-purpose timers (TIM2, TIM15, TIM16) There are up to three synchronizable general-purpose timers embedded in the STM32L432xx (see Table 9 for differences). Each general-purpose timer can be used to generate PWM outputs, or act as a simple time base. • TIM2 It is a full-featured general-purpose timer: TIM2 has a 32-bit auto-reload up/downcounter and 32-bit prescaler.
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Functional overview STM32L432KB STM32L432KC This low-power timer supports the following features: 3.21.
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STM32L432KB STM32L432KC 3.22 Functional overview Real-time clock (RTC) and backup registers The RTC is an independent BCD timer/counter. It supports the following features: • Calendar with subsecond, seconds, minutes, hours (12 or 24 format), week day, date, month, year, in BCD (binary-coded decimal) format. • Automatic correction for 28, 29 (leap year), 30, and 31 days of the month. • Two programmable alarms. • On-the-fly correction from 1 to 32767 RTC clock pulses.
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Functional overview 3.23 STM32L432KB STM32L432KC Inter-integrated circuit interface (I2C) The device embeds 2 I2C. Refer to Table 10: I2C implementation for the features implementation. The I2C bus interface handles communications between the microcontroller and the serial I2C bus. It controls all I2C bus-specific sequencing, protocol, arbitration and timing. The I2C peripheral supports: • • I2C-bus specification and user manual rev.
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STM32L432KB STM32L432KC 3.24 Functional overview Universal synchronous/asynchronous receiver transmitter (USART) The STM32L432xx devices have two embedded universal synchronous receiver transmitters (USART1 and USART2). These interfaces provide asynchronous communication, IrDA SIR ENDEC support, multiprocessor communication mode, single-wire half-duplex communication mode and have LIN Master/Slave capability. They provide hardware management of the CTS and RTS signals, and RS485 Driver Enable.
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Functional overview 3.25 STM32L432KB STM32L432KC Low-power universal asynchronous receiver transmitter (LPUART) The device embeds one Low-Power UART. The LPUART supports asynchronous serial communication with minimum power consumption. It supports half duplex single wire communication and modem operations (CTS/RTS). It allows multiprocessor communication. The LPUART has a clock domain independent from the CPU clock, and can wakeup the system from Stop mode using baudrates up to 220 Kbaud.
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STM32L432KB STM32L432KC 3.26 Functional overview Serial peripheral interface (SPI) Two SPI interfaces allow communication up to 40 Mbits/s in master and up to 24 Mbits/s slave modes, in half-duplex, full-duplex and simplex modes. The 3-bit prescaler gives 8 master mode frequencies and the frame size is configurable from 4 bits to 16 bits. The SPI interfaces support NSS pulse mode, TI mode and Hardware CRC calculation. All SPI interfaces can be served by the DMA controller. 3.
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Functional overview STM32L432KB STM32L432KC Table 12. SAI implementation SAI features Support(1) I2S, LSB or MSB-justified, PCM/DSP, TDM, AC’97 X Mute mode X Stereo/Mono audio frame capability. X 16 slots X Data size configurable: 8-, 10-, 16-, 20-, 24-, 32-bit X FIFO Size X (8 Word) SPDIF X 1. X: supported 3.
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STM32L432KB STM32L432KC Functional overview The CAN peripheral supports: • Supports CAN protocol version 2.0 A, B Active • Bit rates up to 1 Mbit/s • Transmission • • • 3.
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Functional overview 3.32 STM32L432KB STM32L432KC Quad SPI memory interface (QUADSPI) The Quad SPI is a specialized communication interface targeting single, dual or quad SPI flash memories.
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STM32L432KB STM32L432KC Functional overview 3.33 Development support 3.33.1 Serial wire JTAG debug port (SWJ-DP) The ARM SWJ-DP interface is embedded, and is a combined JTAG and serial wire debug port that enables either a serial wire debug or a JTAG probe to be connected to the target.
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Pinouts and pin description 4 STM32L432KB STM32L432KC Pinouts and pin description 966 3+ %227 3% 3% 3% 3% 3% 3$ Figure 4. STM32L432Kx UFQFPN32 pinout(1) 9'' 3$ 3& 26& B,1 3$ 3& 26& B287 3$ 1567 3$ 9''$ 95() 3$ 3$ &.B,1 3$ 3$ 3$ 3$ 9'' 3$ 3$ 3$ 3$ 3$ 3% 3% 966 8)4)31 06Y 9 1.
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STM32L432KB STM32L432KC Pinouts and pin description 2 PC14OSC32_I N (PC14) I/O FT 3 PC15OSC32_ OUT (PC15) I/O FT 4 NRST I/O RST - - - 5 VDDA/VR EF+ S - - - - 6 PA0/ CK_IN - TIM2_CH1, USART2_CTS, COMP1_OUT, SAI1_EXTCLK, TIM2_ETR, EVENTOUT OPAMP1_VINP, COMP1_INM, ADC1_IN5, RTC_TAMP2, WKUP1, CK_IN - TIM2_CH2, I2C1_SMBA, SPI1_SCK, USART2_RTS_DE, TIM15_CH1N, EVENTOUT OPAMP1_VINM, COMP1_INP, ADC1_IN6 - TIM2_CH3, USART2_TX, LPUART1_TX, QUADSPI_BK1_NCS, COMP2_OUT, TIM15_CH1, EVENTOU
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Pinouts and pin description STM32L432KB STM32L432KC 13 14 I/O - TIM1_CH1N, I2C3_SCL, SPI1_MOSI, QUADSPI_BK1_IO2, COMP2_OUT, EVENTOUT ADC1_IN12 - TIM1_CH2N, SPI1_NSS, USART3_CK, QUADSPI_BK1_IO1, COMP1_OUT, SAI1_EXTCLK, EVENTOUT ADC1_IN15 COMP1_INM, ADC1_IN16 Notes I/O structure Additional functions FT_fa FT_a 15 PB1 I/O FT_a - 16 VSS S - - - - 17 VDD S - - - - - 18 PA8 I/O FT - MCO, TIM1_CH1, USART1_CK, SWPMI1_IO, SAI1_SCK_A, LPTIM2_OUT, EVENTOUT 19 PA9 I/O FT_f
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STM32L432KB STM32L432KC Pinouts and pin description PA14 (JTCKSWCLK) 25 PA15 (JTDI) 26 PB3 (JTDOTRACE SWO) 27 PB4 (NJTRST) 28 PB5 I/O FT (3) JTCK-SWCLK, LPTIM1_OUT, I2C1_SMBA, SWPMI1_RX, SAI1_FS_B, EVENTOUT - FT JTDI, TIM2_CH1, TIM2_ETR, USART2_RX, SPI1_NSS, SPI3_NSS, (3) USART3_RTS_DE, TSC_G3_IO1, SWPMI1_SUSPEND, EVENTOUT - I/O Notes I/O structure 24 Pin functions Pin type UFQFPN32 Pin Number Pin name (function after reset) Table 14.
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Memory mapping 5 STM32L432KB STM32L432KC Memory mapping Figure 5.
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STM32L432KB STM32L432KC Memory mapping Table 17.
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Memory mapping STM32L432KB STM32L432KC Table 17. STM32L432xx memory map and peripheral register boundary addresses(1) (continued) Bus APB2 Boundary address Size(bytes) 0x4001 1C00 - 0x4001 1FFF 1 KB FIREWALL 0x4001 0800- 0x4001 1BFF 5 KB Reserved 0x4001 0400 - 0x4001 07FF 1 KB EXTI 0x4001 0200 - 0x4001 03FF 0x4001 0030 - 0x4001 01FF COMP 1 KB 0x4001 0000 - 0x4001 002F APB1 60/155 Downloaded from Arrow.com.
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STM32L432KB STM32L432KC Memory mapping Table 17. STM32L432xx memory map and peripheral register boundary addresses(1) (continued) Bus APB1 Boundary address Size(bytes) Peripheral 0x4000 1000 - 0x4000 13FF 1 KB TIM6 0x4000 0400- 0x4000 0FFF 3 KB Reserved 0x4000 0000 - 0x4000 03FF 1 KB TIM2 1. The gray color is used for reserved boundary addresses. DocID028798 Rev 3 61/155 61 Downloaded from Arrow.com.
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Electrical characteristics STM32L432KB STM32L432KC 6 Electrical characteristics 6.1 Parameter conditions Unless otherwise specified, all voltages are referenced to VSS. 6.1.1 Minimum and maximum values Unless otherwise specified, the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at TA = 25 °C and TA = TAmax (given by the selected temperature range).
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STM32L432KB STM32L432KC 6.1.6 Electrical characteristics Power supply scheme Figure 8. Power supply scheme ĂĐŬƵƉ ĐŝƌĐƵŝƚƌǇ ;>^ ͕ Zd ͕ ĂĐŬƵƉ ƌĞŐŝƐƚĞƌƐͿ ϭ͘ϱϱ ʹ ϯ͘ϲ s 9'' 9&25( Q [ 9'' ZĞŐƵůĂƚŽƌ Khd Q [ Q) *3,2V /E [ ) /HYHO VKLIWHU 9'',2 ,2 ORJLF <ĞƌŶĞů ůŽŐŝĐ ; Wh͕ ŝŐŝƚĂů Θ DĞŵŽƌŝĞƐͿ Q [ 966 9''$ 9''$ 95() ϭϬ Ŷ& ) ϭϬϬ Ŷ& ) 95() 95() $'&V '$&V 23$03V &203V 966$ 06Y 9 Caution: Each power supply pair (VDD/VSS, VDDA/VSSA etc.
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Electrical characteristics 6.1.7 STM32L432KB STM32L432KC Current consumption measurement Figure 9. Current consumption measurement scheme ,''B86% 9''86% ,'' 9'' ,''$ 9''$ 06Y 9 The IDD_ALL parameters given in Table 25 to Table 37 represent the total MCU consumption including the current supplying VDD, VDDA, VDDUSB and VBAT. 6.
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STM32L432KB STM32L432KC Electrical characteristics 1. All main power (VDD, VDDA, VDDUSB,) and ground (VSS, VSSA) pins must always be connected to the external power supply, in the permitted range. 2. VIN maximum must always be respected. Refer to Table 19: Current characteristics for the maximum allowed injected current values. 3. This formula has to be applied only on the power supplies related to the IO structure described in the pin definition table. 4.
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Electrical characteristics STM32L432KB STM32L432KC 6.3 Operating conditions 6.3.1 General operating conditions Table 21. General operating conditions Symbol Parameter Conditions Min Max fHCLK Internal AHB clock frequency - 0 80 fPCLK1 Internal APB1 clock frequency - 0 80 fPCLK2 Internal APB2 clock frequency - 0 80 Standard operating voltage - VDD VDDA Analog supply voltage 1.71 (1) ADC or COMP used 1.62 DAC or OPAMP used 1.
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STM32L432KB STM32L432KC Electrical characteristics 5. In low-power dissipation state, TA can be extended to this range as long as TJ does not exceed TJmax (see Section 7.2: Thermal characteristics). 6.3.2 Operating conditions at power-up / power-down The parameters given in Table 22 are derived from tests performed under the ambient temperature condition summarized in Table 21. Table 22.
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Electrical characteristics STM32L432KB STM32L432KC Table 23. Embedded reset and power control block characteristics (continued) Conditions(1) Min Typ Max Rising edge 2.41 2.46 2.51 Falling edge 2.31 2.36 2.41 Rising edge 2.56 2.61 2.66 Falling edge 2.47 2.52 2.57 Rising edge 2.69 2.74 2.79 Falling edge 2.59 2.64 2.69 Rising edge 2.85 2.91 2.96 Falling edge 2.75 2.81 2.86 Rising edge 2.92 2.98 3.04 Falling edge 2.84 2.90 2.
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STM32L432KB STM32L432KC 6.3.4 Electrical characteristics Embedded voltage reference The parameters given in Table 24 are derived from tests performed under the ambient temperature and supply voltage conditions summarized in Table 21: General operating conditions. Table 24. Embedded internal voltage reference Symbol VREFINT Parameter Conditions Internal reference voltage –40 °C < TA < +130 °C Min Typ Max Unit 1.182 1.212 1.
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Electrical characteristics STM32L432KB STM32L432KC Figure 10. VREFINT versus temperature 9 0HDQ 70/155 Downloaded from Arrow.com.
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STM32L432KB STM32L432KC 6.3.5 Electrical characteristics Supply current characteristics The current consumption is a function of several parameters and factors such as the operating voltage, ambient temperature, I/O pin loading, device software configuration, operating frequencies, I/O pin switching rate, program location in memory and executed binary code. The current consumption is measured as described in Figure 9: Current consumption measurement scheme.
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/155 Downloaded from Arrow.com. DocID028798 Rev 3 0.12 8.53 7.7 6.86 5.13 3.46 2.63 1.8 211 117 58.5 30 100 kHz 80 MHz 72 MHz 64 MHz Range 1 48 MHz 32 MHz 24 MHz 16 MHz 2 MHz 1 MHz 400 kHz 100 kHz 1. Guaranteed by characterization results, unless otherwise specified. 0.2 0.29 2 MHz 0.81 8 MHz 0.46 1.5 16 MHz 4 MHz 2.37 26 MHz 41.1 70.4 134 230 1.81 2.64 3.48 5.16 6.9 7.73 8.56 0.13 0.21 0.3 0.47 0.82 1.52 2.
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Downloaded from Arrow.com. Supply current in fHCLK = fMSI Low-power all peripherals disable run IDD_ALL (Run) IDD_ALL (LPRun) 1.05 8 MHz DocID028798 Rev 3 4.56 3.45 2.48 310 157 72.6 32.3 32 MHz 24 MHz 16 MHz 2 MHz 1 MHz 400 kHz 100 kHz 1. Guaranteed by characterization results, unless otherwise specified. 6.36 Range 1 48 MHz 80 MHz 7.63 100 kHz 7.74 0.12 8.56 1 MHz 64 MHz 0.36 0.23 2 MHz 0.6 1.88 16 MHz 4 MHz 2.66 26 MHz 46 89 173 317 2.51 3.48 4.6 6.4 7.68 7.79 8.61 0.
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/155 Downloaded from Arrow.com. fHCLK = fMSI all peripherals disable FLASH in power-down Supply current in low-power run mode DocID028798 Rev 3 Range 1 49.2 21.5 100 kHz 2 MHz 400 kHz 205 16 MHz 111 1.82 24 MHz 1 MHz 3.51 2.66 32 MHz 5.19 6.95 64 MHz 48 MHz 7.79 8.63 80 MHz 72 MHz 0.2 0.12 1 MHz 100 kHz 0.29 2 MHz 0.82 8 MHz 0.47 1.54 4 MHz 2.43 2.42 26 MHz 16 MHz 33.3 62.7 126 228 1.84 2.68 3.53 5.22 6.99 7.83 8.68 0.13 0.21 0.3 0.48 0.84 1.
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STM32L432KB STM32L432KC Electrical characteristics Table 28.
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Electrical characteristics STM32L432KB STM32L432KC Table 29.
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Downloaded from Arrow.com. DocID028798 Rev 3 IDD_ALL (Sleep) 0.11 2.23 2.02 1.82 1.34 0.93 0.73 0.53 71.8 45.0 27.0 22.8 72 MHz 64 MHz Range 1 48 MHz 32 MHz 24 MHz 16 MHz 2 MHz 1 MHz 400 kHz 100 kHz 0.13 1 MHz 80 MHz 0.16 2 MHz 8 MHz 0.20 0.46 0.29 16 MHz 4 MHz 0.68 26 MHz 30.9 40.7 57.3 80.7 0.55 0.75 0.95 1.36 1.84 2.04 2.25 0.13 0.15 0.17 0.21 0.30 0.48 0.69 25 °C 55 °C fHCLK 100 kHz Range 2 Voltage scaling 1.
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/155 Downloaded from Arrow.com. Supply current in low-power sleep mode IDD_ALL (LPSleep) Voltage scaling fHCLK = fMSI all peripherals disable 58.7 39.4 20.8 14.3 2 MHz 1 MHz 400 kHz 100 kHz DocID028798 Rev 3 IDD_ALL (Stop 2) RTC clocked by LSI - - Conditions RTC clocked by LSE quartz(2) in low drive mode Supply current in RTC clocked by LSE Stop 2 mode, bypassed at 32768 Hz RTC enabled Supply current in Stop 2 mode, RTC disabled IDD_ALL (Stop 2 with RTC) Parameter Symbol 55.1 62.
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Downloaded from Arrow.com. Parameter 3V 3V 3V Wakeup clock is MSI = 4 MHz, voltage Range 2. See (3). Wakeup clock is HSI16 = 16 MHz, voltage Range 1. See (3). VDD Wakeup clock is MSI = 48 MHz, voltage Range 1. See (3). - Conditions 1.54 1.52 1.85 - - - 85 °C TYP - - - - - - - - - 105 °C 125 °C 25 °C - - - 55 °C 3. Wakeup with code execution from Flash. Average value given for a typical wakeup time as specified in Table 39: Low-power mode wakeup timings.
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/155 Downloaded from Arrow.com. Supply current in Stop 1 mode, RTC disabled IDD_ALL (Stop 1) RTC clocked by LSI - - Conditions 4.7 4.95 1.8 V 2.4 V DocID028798 Rev 3 1.22 1.20 3V 3V - - - 13 12.6 12.4 43.6 - - - 44.8 44.1 43.8 43.7 48.8 45.4 44.4 44 45.3 44.6 44.2 43.9 44.8 44.1 43.8 - - - 101 99.6 99.3 99.1 103 99.1 97.6 96.9 99.5 98.1 97.4 96.8 98.9 97.7 97 96.4 204 - - - - - - - 216 209 206 205 210 207 206 205 210 207 205 9.
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Downloaded from Arrow.com. Supply current in Stop 0 mode, RTC disabled IDD_ALL (Stop 0) 108 110 111 114 1.8 V 2.4 V 3V 3.6 V 2. Guaranteed by test in production. 125 123 121 119 25 °C 55 °C VDD Conditions 1. Guaranteed by characterization results, unless otherwise specified. Parameter Symbol 163 161 160 158 85 °C TYP 227 224 223 221 355 352 349 347 142 139 136 133 105 °C 125 °C 25 °C Table 35.
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/155 Downloaded from Arrow.com. IDD_ALL (Standby) IDD_ALL (Standby with RTC) Supply current in Standby mode (backup registers retained), RTC disabled Supply current in Standby mode (backup registers retained), RTC enabled Parameter Symbol DocID028798 Rev 3 219 364 142 249 1.8 V 2.4 V 548 715 281 388 535 836 1.8 V 2.4 V RTC clocked by LSE quartz (3) in low drive mode 3 V 3.6 V 1 048 423 670 404 742 3V 126 - - - 655 521 2.4 V - 865 342 1.8 V 978 3V 771 3.
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Downloaded from Arrow.com. Supply current to be added in Standby mode when SRAM2 is retained Supply current during wakeup from Standby mode Parameter Wakeup clock is MSI = 4 MHz. See (5). - - Conditions 178 184 3V 3.
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/155 Downloaded from Arrow.com. Supply current in Shutdown mode (backup registers retained) RTC enabled IDD_ALL (Shutdown with RTC) Wakeup clock is MSI = 4 MHz. See (3). RTC clocked by LSE quartz (2) in low drive mode RTC clocked by LSE bypassed at 32768 Hz - Conditions 744 3.
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STM32L432KB STM32L432KC Electrical characteristics I/O system current consumption The current consumption of the I/O system has two components: static and dynamic. I/O static current consumption All the I/Os used as inputs with pull-up generate current consumption when the pin is externally held low. The value of this current consumption can be simply computed by using the pull-up/pull-down resistors values given in Table 57: I/O static characteristics.
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Electrical characteristics STM32L432KB STM32L432KC On-chip peripheral current consumption The current consumption of the on-chip peripherals is given in Table 38.
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STM32L432KB STM32L432KC Electrical characteristics Table 38. Peripheral current consumption (continued) Range 1 Range 2 Low-power run and sleep USB FS independent clock domain 2.9 N/A N/A USB FS clock domain 2.3 N/A N/A I2C1 independent clock domain 3.5 2.8 3.4 I2C1 clock domain 1.1 0.9 1.0 I2C3 independent clock domain 2.9 2.3 2.5 I2C3 clock domain 0.9 0.4 0.8 LPUART1 independent clock domain 1.9 1.6 1.8 LPUART1 clock domain 0.6 0.6 0.
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Electrical characteristics STM32L432KB STM32L432KC Table 38. Peripheral current consumption (continued) Range 1 Range 2 Low-power run and sleep TIM1 8.1 6.5 7.6 TIM15 3.7 3.0 3.4 TIM16 2.7 2.1 2.6 USART1 independent clock domain 4.8 4.2 4.6 USART1 clock domain 1.5 1.3 1.7 All APB2 on 24.2 19.9 22.6 86.1 65.1 80.9 Peripheral APB2 ALL Unit µA/MHz 1. The BusMatrix is automatically active when at least one master is ON (CPU, DMA). 2.
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STM32L432KB STM32L432KC Electrical characteristics Table 39.
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Electrical characteristics STM32L432KB STM32L432KC Table 39. Low-power mode wakeup timings(1) (continued) Symbol Parameter Conditions Typ Max Wakeup clock MSI = 48 MHz 8.02 9.24 Wakeup clock HSI16 = 16 MHz 7.66 8.95 Wakeup clock MSI = 24 MHz 8.5 9.54 Wakeup clock HSI16 = 16 MHz 7.75 8.95 Wakeup clock MSI = 4 MHz 12.06 13.16 Wakeup clock MSI = 48 MHz 5.45 6.79 Wakeup clock HSI16 = 16 MHz 6.9 7.98 Wakeup clock MSI = 24 MHz 6.3 7.36 Wakeup clock HSI16 = 16 MHz 6.9 7.
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STM32L432KB STM32L432KC 6.3.7 Electrical characteristics External clock source characteristics High-speed external user clock generated from an external source In bypass mode the HSE oscillator is switched off and the input pin is a standard GPIO. The external clock signal has to respect the I/O characteristics in Section 6.3.14. However, the recommended clock input waveform is shown in Figure 11: High-speed external clock source AC timing diagram. Table 42.
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Electrical characteristics STM32L432KB STM32L432KC Low-speed external user clock generated from an external source In bypass mode the LSE oscillator is switched off and the input pin is a standard GPIO. The external clock signal has to respect the I/O characteristics in Section 6.3.14. However, the recommended clock input waveform is shown in Figure 12. Table 43.
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STM32L432KB STM32L432KC Electrical characteristics Table 44. LSE oscillator characteristics (fLSE = 32.768 kHz)(1) Symbol IDD(LSE) Conditions(2) Parameter LSE current consumption Maximum critical crystal Gmcritmax gm Min Typ Max LSEDRV[1:0] = 00 Low drive capability - 250 - LSEDRV[1:0] = 01 Medium low drive capability - 315 - LSEDRV[1:0] = 10 Medium high drive capability - 500 - LSEDRV[1:0] = 11 High drive capability - 630 - LSEDRV[1:0] = 00 Low drive capability - - 0.
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Electrical characteristics 6.3.8 STM32L432KB STM32L432KC Internal clock source characteristics The parameters given in Table 45 are derived from tests performed under ambient temperature and supply voltage conditions summarized in Table 21: General operating conditions. The provided curves are characterization results, not tested in production. High-speed internal (HSI16) RC oscillator Table 45.
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STM32L432KB STM32L432KC Electrical characteristics Figure 14. HSI16 frequency versus temperature 0+] PLQ PHDQ & PD[ 06Y 9 DocID028798 Rev 3 95/155 147 Downloaded from Arrow.com.
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Electrical characteristics STM32L432KB STM32L432KC Multi-speed internal (MSI) RC oscillator Table 46. MSI oscillator characteristics(1) Symbol Parameter Conditions Min Typ Max Range 0 98.7 100 101.3 Range 1 197.4 200 202.6 Range 2 394.8 400 405.2 Range 3 789.6 800 810.4 Range 4 0.987 1 1.013 Range 5 1.974 2 2.026 Range 6 3.948 4 4.052 Range 7 7.896 8 8.104 Range 8 15.79 16 16.21 Range 9 23.69 24 24.31 Range 10 31.58 32 32.42 Range 11 47.38 48 48.
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STM32L432KB STM32L432KC Electrical characteristics Table 46. MSI oscillator characteristics(1) (continued) Symbol Parameter Conditions Min Typ VDD=1.62 V to 3.6 V -1.2 - VDD=2.4 V to 3.6 V -0.5 - VDD=1.62 V to 3.6 V -2.5 - VDD=2.4 V to 3.6 V -0.8 - VDD=1.62 V to 3.6 V -5 - VDD=2.4 V to 3.6 V -1.
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Electrical characteristics STM32L432KB STM32L432KC Table 46. MSI oscillator characteristics(1) (continued) Symbol IDD(MSI)(6) Parameter MSI oscillator power consumption Conditions MSI and PLL mode Min Typ Max Range 0 - - 0.6 1 Range 1 - - 0.8 1.2 Range 2 - - 1.2 1.7 Range 3 - - 1.9 2.5 Range 4 - - 4.7 6 Range 5 - - 6.5 9 Range 6 - - 11 15 Range 7 - - 18.
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STM32L432KB STM32L432KC Electrical characteristics Figure 15. Typical current consumption versus MSI frequency High-speed internal 48 MHz (HSI48) RC oscillator Table 47. HSI48 oscillator characteristics(1) Symbol Parameter fHSI48 HSI48 Frequency TRIM HSI48 user trimming step USER TRIM COVERAGE Conditions VDD=3.
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Electrical characteristics STM32L432KB STM32L432KC Table 47. HSI48 oscillator characteristics(1) (continued) Symbol Parameter Conditions Min Typ Max Unit NT jitter Next transition jitter Accumulated jitter on 28 cycles(4) - - +/-0.15(2) - ns PT jitter Paired transition jitter Accumulated jitter on 56 cycles(4) - - +/-0.25(2) - ns 1. VDD = 3 V, TA = –40 to 125°C unless otherwise specified. 2. Guaranteed by design. 3. Guaranteed by characterization results. 4.
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STM32L432KB STM32L432KC 6.3.9 Electrical characteristics PLL characteristics The parameters given in Table 49 are derived from tests performed under temperature and VDD supply voltage conditions summarized in Table 21: General operating conditions. Table 49. PLL, PLLSAI1 characteristics(1) Symbol fPLL_IN Parameter Conditions Min Typ Max Unit PLL input clock(2) - 4 - 16 MHz PLL input clock duty cycle - 45 - 55 % Voltage scaling Range 1 3.0968 - 80 Voltage scaling Range 2 3.
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Electrical characteristics 6.3.10 STM32L432KB STM32L432KC Flash memory characteristics Table 50. Flash memory characteristics(1) Symbol Parameter Conditions Typ Max Unit tprog 64-bit programming time - 81.69 90.76 µs tprog_row one row (32 double word) programming time normal programming 2.61 2.90 fast programming 1.91 2.12 tprog_page one page (2 Kbyte) programming time normal programming 20.91 23.24 fast programming 15.29 16.98 22.02 24.47 normal programming 5.35 5.
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STM32L432KB STM32L432KC 6.3.11 Electrical characteristics EMC characteristics Susceptibility tests are performed on a sample basis during device characterization. Functional EMS (electromagnetic susceptibility) While a simple application is executed on the device (toggling 2 LEDs through I/O ports). the device is stressed by two electromagnetic events until a failure occurs.
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Electrical characteristics STM32L432KB STM32L432KC Prequalification trials Most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1 second. To complete these trials, ESD stress can be applied directly on the device, over the range of specification values.
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STM32L432KB STM32L432KC Electrical characteristics Static latch-up Two complementary static tests are required on six parts to assess the latch-up performance: • A supply overvoltage is applied to each power supply pin. • A current injection is applied to each input, output and configurable I/O pin. These tests are compliant with EIA/JESD 78A IC latch-up standard. Table 55. Electrical sensitivities Symbol LU 6.3.
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Electrical characteristics 6.3.14 STM32L432KB STM32L432KC I/O port characteristics General input/output characteristics Unless otherwise specified, the parameters given in Table 57 are derived from tests performed under the conditions summarized in Table 21: General operating conditions. All I/Os are designed as CMOS- and TTL-compliant. Table 57. I/O static characteristics Symbol VIL(1) VIH(1) Vhys(3) Parameter Max - - 0.3xVDDIOx (2) I/O input low level voltage 1.62 V
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STM32L432KB STM32L432KC Electrical characteristics Table 57. I/O static characteristics (continued) Symbol Parameter Conditions RPD Weak pull-down VIN = VDDIOx equivalent resistor(8) CIO I/O pin capacitance Min Typ Max Unit 25 40 55 kΩ - 5 - pF - 1. Refer to Figure 17: I/O input characteristics. 2. Tested in production. 3. Guaranteed by design. 4. This value represents the pad leakage of the IO itself.
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Electrical characteristics STM32L432KB STM32L432KC In the user application, the number of I/O pins which can drive current must be limited to respect the absolute maximum rating specified in Section 6.2: • The sum of the currents sourced by all the I/Os on VDDIOx, plus the maximum consumption of the MCU sourced on VDD, cannot exceed the absolute maximum rating ΣIVDD (see Table 18: Voltage characteristics).
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STM32L432KB STM32L432KC Electrical characteristics Unless otherwise specified, the parameters given are derived from tests performed under the ambient temperature and supply voltage conditions summarized in Table 21: General operating conditions. Table 59. I/O AC characteristics(1)(2) Speed Symbol Fmax Parameter Maximum frequency 00 Tr/Tf Fmax Output rise and fall time Maximum frequency 01 Tr/Tf Output rise and fall time Conditions Min Max C=50 pF, 2.7 V≤VDDIOx≤3.6 V - 5 C=50 pF, 1.
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Electrical characteristics STM32L432KB STM32L432KC Table 59. I/O AC characteristics(1)(2) (continued) Speed Symbol Fmax Parameter Maximum frequency 10 Tr/Tf Fmax Output rise and fall time Maximum frequency 11 Tr/Tf Fm+ Fmax Tf Output rise and fall time Maximum frequency (4) Output fall time Conditions Min Max C=50 pF, 2.7 V≤VDDIOx≤3.6 V - 50 C=50 pF, 1.62 V≤VDDIOx≤2.7 V - 25 C=50 pF, 1.08 V≤VDDIOx≤1.62 V - 5 C=10 pF, 2.7 V≤VDDIOx≤3.6 V - 100(3) C=10 pF, 1.62 V≤VDDIOx≤2.
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STM32L432KB STM32L432KC Electrical characteristics Figure 18. I/O AC characteristics definition(1) W I ,2 RXW W U ,2 RXW 7 0D[LPXP IUHTXHQF\ LV DFKLHYHG LI W W U I 7 DQG LI WKH GXW\ F\FOH LV ZKHQ ORDGHG E\ WKH VSHFLILHG FDSDFLWDQFH 06 9 1. Refer to Table 59: I/O AC characteristics. 6.3.15 NRST pin characteristics The NRST pin input driver uses the CMOS technology. It is connected to a permanent pullup resistor, RPU.
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Electrical characteristics STM32L432KB STM32L432KC Figure 19. Recommended NRST pin protection ([WHUQDO UHVHW FLUFXLW 9'' 1567 538 ,QWHUQDO UHVHW )LOWHU ) 06 9 1. The reset network protects the device against parasitic resets. 2. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in Table 60: NRST pin characteristics. Otherwise the reset will not be taken into account by the device. 3.
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STM32L432KB STM32L432KC 6.3.17 Electrical characteristics Analog-to-Digital converter characteristics Unless otherwise specified, the parameters given in Table 62 are preliminary values derived from tests performed under ambient temperature, fPCLK frequency and VDDA supply voltage conditions summarized in Table 21: General operating conditions. Note: It is recommended to perform a calibration after each power-up. Table 62.
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Electrical characteristics STM32L432KB STM32L432KC Table 62. ADC characteristics(1) (2) (continued) Symbol Parameter tLATR Trigger conversion latency Regular and injected channels without conversion abort Conditions Min Typ Max CKMODE = 00 1.5 2 2.5 CKMODE = 01 - - 2.0 CKMODE = 10 - - 2.25 CKMODE = 11 - - 2.125 2.5 3 3.5 - - 3.0 - - 3.25 - - 3.125 0.03125 - 8.00625 µs - 2.5 - 640.5 1/fADC - - - 20 µs 0.1875 - 8.
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STM32L432KB STM32L432KC Electrical characteristics Table 63. Maximum ADC RAIN(1)(2) Resolution 12 bits 10 bits 8 bits 6 bits Sampling cycle @80 MHz Sampling time [ns] @80 MHz 2.5 RAIN max (Ω) Fast channels(3) Slow channels(4) 31.25 100 N/A 6.5 81.25 330 100 12.5 156.25 680 470 24.5 306.25 1500 1200 47.5 593.75 2200 1800 92.5 1156.25 4700 3900 247.5 3093.75 12000 10000 640.5 8006.75 39000 33000 2.5 31.25 120 N/A 6.5 81.25 390 180 12.5 156.25 820 560 24.
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Electrical characteristics STM32L432KB STM32L432KC 2. The I/O analog switch voltage booster is enable when VDDA < 2.4 V (BOOSTEN = 1 in the SYSCFG_CFGR1 when VDDA < 2.4V). It is disable when VDDA ≥ 2.4 V. 3. Fast channels are: PC0, PC1, PC2, PC3, PA0, PA1. 4. Slow channels are: all ADC inputs except the fast channels. 116/155 Downloaded from Arrow.com.
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STM32L432KB STM32L432KC Electrical characteristics Table 64. ADC accuracy - limited test conditions 1(1)(2)(3) Symbol Parameter ET Total unadjusted error EO Conditions(4) Single ended Differential Single ended Offset error Differential Single ended EG Gain error Differential ED EL Differential linearity ADC clock frequency ≤ error 80 MHz, Sampling rate ≤ 5.
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Electrical characteristics STM32L432KB STM32L432KC Table 64. ADC accuracy - limited test conditions 1(1)(2)(3) (continued) Symbol THD Conditions(4) Parameter Total harmonic distortion ADC clock frequency ≤ Single 80 MHz, ended Sampling rate ≤ 5.33 Msps, VDDA = VREF+ = 3 V, Differential TA = 25 °C Min Typ Max Unit Fast channel (max speed) - -74 -73 Slow channel (max speed) - -74 -73 Fast channel (max speed) - -79 -76 Slow channel (max speed) - -79 -76 dB 1. Guaranteed by design. 2.
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STM32L432KB STM32L432KC Electrical characteristics Table 65. ADC accuracy - limited test conditions 2(1)(2)(3) Symbol Parameter ET Total unadjusted error EO Conditions(4) Single ended Differential Single ended Offset error Differential Single ended EG Gain error Differential ED EL Differential linearity error ADC clock frequency ≤ 80 MHz, Sampling rate ≤ 5.
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Electrical characteristics STM32L432KB STM32L432KC Table 65. ADC accuracy - limited test conditions 2(1)(2)(3) (continued) Symbol THD Conditions(4) Parameter Total harmonic distortion Fast channel (max speed) Single ADC clock frequency ≤ ended Slow channel (max speed) 80 MHz, Sampling rate ≤ 5.33 Msps, Fast channel (max speed) Differential 2 V ≤ VDDA Slow channel (max speed) Min Typ Max Unit - -74 -65 - -74 -67 - -79 -70 - -79 -71 dB 1. Guaranteed by design. 2.
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STM32L432KB STM32L432KC Electrical characteristics Table 66. ADC accuracy - limited test conditions 3(1)(2)(3) Symbol Parameter ET Total unadjusted error EO Conditions(4) Single ended Differential Single ended Offset error Differential Single ended EG Gain error Differential ED EL Differential linearity ADC clock frequency ≤ error 80 MHz, Sampling rate ≤ 5.33 Msps, 1.65 V ≤ VDDA = VREF+ ≤ 3.
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Electrical characteristics STM32L432KB STM32L432KC Table 66. ADC accuracy - limited test conditions 3(1)(2)(3) (continued) Symbol THD Conditions(4) Parameter Total harmonic distortion ADC clock frequency ≤ Single 80 MHz, ended Sampling rate ≤ 5.33 Msps, 1.65 V ≤ VDDA = VREF+ ≤ Differential 3.6 V, Voltage scaling Range 1 Min Typ Max Unit Fast channel (max speed) - -69 -67 Slow channel (max speed) - -71 -67 Fast channel (max speed) - -72 -71 Slow channel (max speed) - -72 -71 dB 1.
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STM32L432KB STM32L432KC Electrical characteristics Table 67. ADC accuracy - limited test conditions 4(1)(2)(3) Symbol Parameter ET Total unadjusted error EO Conditions(4) Single ended Differential Single ended Offset error Differential Single ended EG Gain error Differential ED EL Differential linearity ADC clock frequency ≤ error 26 MHz, 1.65 V ≤ VDDA = VREF+ ≤ 3.
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Electrical characteristics STM32L432KB STM32L432KC Table 67. ADC accuracy - limited test conditions 4(1)(2)(3) (continued) Symbol THD Conditions(4) Parameter ADC clock frequency ≤ 26 MHz, 1.65 V ≤ VDDA = VREF+ ≤ 3.6 V, Voltage scaling Range 2 Total harmonic distortion Single ended Differential Min Typ Max Unit Fast channel (max speed) - -71 -69 Slow channel (max speed) - -71 -69 Fast channel (max speed) - -73 -72 Slow channel (max speed) - -73 -72 dB 1. Guaranteed by design. 2.
PAGE 125
STM32L432KB STM32L432KC Electrical characteristics Figure 21. Typical connection diagram using the ADC 9''$ 97 5$,1 9$,1 6DPSOH DQG KROG $'& FRQYHUWHU 5$'& $,1[ &SDUDVLWLF 97 ,ONJ ELW FRQYHUWHU &$'& 06 9 1. Refer to Table 62: ADC characteristics for the values of RAIN and CADC. 2.
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Electrical characteristics 6.3.18 STM32L432KB STM32L432KC Digital-to-Analog converter characteristics Table 68. DAC characteristics(1) Symbol VDDA VREF+ VREF- Parameter Analog supply voltage for DAC ON Positive reference voltage Conditions Min Typ DAC output buffer OFF, DAC_OUT pin not connected (internal connection only) 1.71 - Other modes 1.80 - DAC output buffer OFF, DAC_OUT pin not connected (internal connection only) 1.71 - Other modes 1.80 Negative reference voltage Max 3.
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STM32L432KB STM32L432KC Electrical characteristics Table 68. DAC characteristics(1) (continued) Symbol TW_to_W tSAMP Parameter Conditions Typ Max Unit - - µs - 0.7 3.5 - 10.5 18 - 2 3.5 µs - - -(3) nA 5.2 7 8.8 pF 50 - - µs VREF+ = 3.6 V - 1500 - VREF+ = 1.8 V - 750 - No load, middle code (0x800) - 315 500 No load, worst code (0xF1C) - 450 670 No load, middle code (0x800) - - 0.
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Electrical characteristics STM32L432KB STM32L432KC Table 68.
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STM32L432KB STM32L432KC Table 69. DAC accuracy(1) .
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Electrical characteristics STM32L432KB STM32L432KC Table 69. DAC accuracy(1) (continued) Symbol Parameter SINAD Signal-to-noise and distortion ratio ENOB Effective number of bits Conditions Min Typ Max DAC output buffer ON CL ≤ 50 pF, RL ≥ 5 kΩ, 1 kHz - 70.4 - DAC output buffer OFF CL ≤ 50 pF, no RL, 1 kHz - 71 - DAC output buffer ON CL ≤ 50 pF, RL ≥ 5 kΩ, 1 kHz - 11.4 - DAC output buffer OFF CL ≤ 50 pF, no RL, 1 kHz - Unit dB bits 11.5 - 1. Guaranteed by design. 2.
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STM32L432KB STM32L432KC 6.3.19 Electrical characteristics Comparator characteristics Table 70. COMP characteristics(1) Symbol Conditions Min Typ Max Analog supply voltage - 1.62 - 3.6 Comparator input voltage range - 0 - VDDA V VBG(2) Scaler input voltage - VSC Scaler offset voltage - VDDA VIN IDDA(SCALER) Parameter VREFINT - ±5 ±10 mV BRG_EN=0 (bridge disable) - 200 300 nA BRG_EN=1 (bridge enable) - 0.8 1 µA - 100 200 µs VDDA ≥ 2.7 V - - 5 VDDA < 2.
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Electrical characteristics STM32L432KB STM32L432KC Table 70.
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STM32L432KB STM32L432KC Electrical characteristics Table 71.
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Electrical characteristics STM32L432KB STM32L432KC Table 71.
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STM32L432KB STM32L432KC Electrical characteristics Table 71.
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Electrical characteristics STM32L432KB STM32L432KC Refer to Section 6.3.14: I/O port characteristics for details on the input/output alternate function characteristics (output compare, input capture, external clock, PWM output). Table 73. TIMx(1) characteristics Symbol tres(TIM) Parameter Timer resolution time Conditions Min Max Unit - 1 - tTIMxCLK fTIMxCLK = 80 MHz 12.5 - ns 0 fTIMxCLK/2 MHz 0 40 MHz TIMx (except TIM2) - 16 TIM2 - 32 - 1 65536 tTIMxCLK fTIMxCLK = 80 MHz 0.
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STM32L432KB STM32L432KC 6.3.23 Electrical characteristics Communication interfaces characteristics I2C interface characteristics The I2C interface meets the timings requirements of the I2C-bus specification and user manual rev. 03 for: • Standard-mode (Sm): with a bit rate up to 100 kbit/s • Fast-mode (Fm): with a bit rate up to 400 kbit/s • Fast-mode Plus (Fm+): with a bit rate up to 1 Mbit/s.
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Electrical characteristics STM32L432KB STM32L432KC SPI characteristics Unless otherwise specified, the parameters given in Table 77 for SPI are derived from tests performed under the ambient temperature, fPCLKx frequency and supply voltage conditions summarized in Table 21: General operating conditions. • Output speed is set to OSPEEDRy[1:0] = 11 • Capacitive load C = 30 pF • Measurement points are done at CMOS levels: 0.5 ₓ VDD Refer to Section 6.3.
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STM32L432KB STM32L432KC Electrical characteristics Table 77. SPI characteristics(1) (continued) Symbol tv(SO) Parameter Data output valid time tv(MO) th(SO) Data output hold time th(MO) Conditions Min Typ Max Slave mode 2.7 < VDD < 3.6 V Voltage Range 1 - 12.5 13.5 Slave mode 1.71 < VDD < 3.6 V Voltage Range 1 - 12.5 24 Slave mode 1.71 < VDD < 3.6 V Voltage Range 2 - 12.5 33 Master mode - 4.5 6 Slave mode 7 - - Master mode 0 - - Unit ns ns 1.
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Electrical characteristics STM32L432KB STM32L432KC Figure 24. SPI timing diagram - slave mode and CPHA = 1 166 LQSXW WF 6&. WVX 166 WZ 6&.+ WD 62 WZ 6&./ WI 6&. WK 166 6&. LQSXW &3+$ &32/ &3+$ &32/ 0,62 RXWSXW WY 62 WK 62 )LUVW ELW 287 WVX 6, 1H[W ELWV 287 WU 6&. WGLV 62 /DVW ELW 287 WK 6, 026, LQSXW )LUVW ELW ,1 1H[W ELWV ,1 /DVW ELW ,1 06Y 9 1. Measurement points are done at CMOS levels: 0.3 VDD and 0.7 VDD. Figure 25.
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STM32L432KB STM32L432KC Electrical characteristics Quad SPI characteristics Unless otherwise specified, the parameters given in Table 78 and Table 79 for Quad SPI are derived from tests performed under the ambient temperature, fAHB frequency and VDD supply voltage conditions summarized in Table 21: General operating conditions, with the following configuration: • Output speed is set to OSPEEDRy[1:0] = 11 • Capacitive load C = 15 or 20 pF • Measurement points are done at CMOS levels: 0.
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Electrical characteristics STM32L432KB STM32L432KC Table 79. QUADSPI characteristics in DDR mode(1) Symbol FCK 1/t(CK) tw(CKH) tw(CKL) Parameter Quad SPI clock frequency Quad SPI clock high and low time Conditions Min Typ Max 1.71 < VDD < 3.6 V, CLOAD = 20 pF Voltage Range 1 - - 40 2 < VDD < 3.6 V, CLOAD = 20 pF Voltage Range 1 - - 48 1.71 < VDD < 3.6 V, CLOAD = 15 pF Voltage Range 1 - - 48 1.71 < VDD < 3.
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STM32L432KB STM32L432KC Electrical characteristics Figure 26. Quad SPI timing diagram - SDR mode WU &. &ORFN W &. WZ &.+ WY 287 WZ &./ WI &. WK 287 'DWD RXWSXW ' ' WV ,1 'DWD LQSXW ' WK ,1 ' ' ' 06Y 9 Figure 27. Quad SPI timing diagram - DDR mode WU &. &ORFN 'DWD RXWSXW W &. WYI 287 WZ &.+ WKU 287 ' WYU 287 ' ' WZ &./ WKI 287 ' WVI ,1 WKI ,1 'DWD LQSXW ' ' WI &.
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Electrical characteristics STM32L432KB STM32L432KC SAI characteristics Unless otherwise specified, the parameters given in Table 80 for SAI are derived from tests performed under the ambient temperature, fPCLKx frequency and VDD supply voltage conditions summarized inTable 21: General operating conditions, with the following configuration: • Output speed is set to OSPEEDRy[1:0] = 10 • Capacitive load C = 30 pF • Measurement points are done at CMOS levels: 0.5 ₓ VDD Refer to Section 6.3.
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STM32L432KB STM32L432KC Electrical characteristics Table 80. SAI characteristics(1) (continued) Symbol tv(SD_B_ST) th(SD_B_ST) tv(SD_A_MT) th(SD_A_MT) Parameter Conditions Data output valid time Data output hold time Data output valid time Data output hold time Min Max Slave transmitter (after enable edge) 2.7 ≤ VDD ≤ 3.6 - 22 Slave transmitter (after enable edge) 1.71 ≤ VDD ≤ 3.6 - 34 Slave transmitter (after enable edge) 10 - Master transmitter (after enable edge) 2.7 ≤ VDD ≤ 3.
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Electrical characteristics STM32L432KB STM32L432KC Figure 29. SAI slave timing waveforms F3#+ 3!)?3#+?8 TW #+(?8 3!)?&3?8 INPUT TW #+,?8 TH &3 TSU &3 TH 3$?34 TV 3$?34 3!)?3$?8 TRANSMIT 3LOT N 3LOT N TSU 3$?32 3!)?3$?8 RECEIVE TH 3$?32 3LOT N -3 6 USB characteristics The STM32L432xx USB interface is fully compliant with the USB specification version 2.0 and is USB-IF certified (for Full-speed device operation). Table 81.
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STM32L432KB STM32L432KC Electrical characteristics SWPMI characteristics The Single Wire Protocol Master Interface (SWPMI) and the associated SWPMI_IO transceiver are compliant with the ETSI TS 102 613 technical specification. Table 82. SWPMI electrical characteristics Symbol Parameter tSWPSTART SWPMI regulator startup time tSWPBIT SWP bit duration Conditions Min Typ - - 300 VCORE voltage range 1 500 - - VCORE voltage range 2 620 - - SWP Class B 2.
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Package information 7 STM32L432KB STM32L432KC Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. 7.1 UFQFPN32 package information Figure 30. UFQFPN32 - 32-pin, 5x5 mm, 0.
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STM32L432KB STM32L432KC Package information Table 83. UFQFPN32 - 32-pin, 5x5 mm, 0.5 mm pitch ultra thin fine pitch quad flat package mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A 0.500 0.550 0.600 0.0197 0.0217 0.0236 A1 - - 0.050 - - 0.0020 A3 - 0.152 - - 0.0060 - b 0.180 0.230 0.280 0.0071 0.0091 0.0110 D 4.900 5.000 5.100 0.1929 0.1969 0.2008 D1 3.400 3.500 3.600 0.1339 0.1378 0.1417 D2 3.400 3.500 3.600 0.1339 0.1378 0.
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Package information STM32L432KB STM32L432KC Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below. Figure 32. UFQFPN32 marking (package top view) 3URGXFW LGHQWLILFDWLRQ / .& < :: $ 'DWH FRGH 5HYLVLRQ FRGH 3LQ LGHQWLILHU 06Y 9 1. Parts marked as ES or E or accompanied by an Engineering Sample notification letter are not yet qualified and therefore not approved for use in production.
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STM32L432KB STM32L432KC 7.2 Package information Thermal characteristics The maximum chip junction temperature (TJmax) must never exceed the values given in Table 21: General operating conditions.
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Part numbering 8 STM32L432KB STM32L432KC Part numbering Table 85.
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STM32L432KB STM32L432KC 9 Revision history Revision history Table 86. Document revision history Date Revision 08-Feb-2016 1 Initial release. 2 Updated document title. Updated Table 1: STM32L432Kx family device features and peripheral counts. Updated Section 3.24: Universal synchronous/asynchronous receiver transmitter (USART). Updated Table 14: STM32L432xx pin definitions. Updated Table 16: Alternate function AF8 to AF15 (for AF0 to AF7 see Table 15). Updated Table 18: Voltage characteristics.
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Revision history STM32L432KB STM32L432KC Table 86. Document revision history (continued) Date 12-Jun-2017 154/155 Downloaded from Arrow.com. Revision 3 (continued) Changes Updated Section 6.1.7: Current consumption measurement. Added footnote to Table 56: I/O current injection susceptibility. Updated Table 57: I/O static characteristics. Updated Section 6.3.17: Analog-to-Digital converter characteristics. Added FADC min in Table 62: ADC characteristics. Updated Table 68: DAC characteristics.
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STM32L432KB STM32L432KC IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement.