Datasheet

ManualsBrandsST ManualsEmbedded Processors & ControllersMicrocontroller 32bit 256KB LQFP

This is information on a product in full production.

June 2019 DS10198 Rev 8 1/270

STM32L476xx

Ultra-low-power Arm

Cortex

-M4 32-bit MCU+FPU, 100DMIPS,

up to 1MB Flash, 128 KB SRAM, USB OTG FS, LCD, ext. SMPS

Datasheet - production data

Features

• Ultra-low-power with FlexPowerControl

– 1.71 V to 3.6 V power supply

– -40 °C to 85/105/125 °C temperature range

– 300 nA in V

BAT

mode: supply for RTC and

32x32-bit backup registers

– 30 nA Shutdown mode (5 wakeup pins)

– 120 nA Standby mode (5 wakeup pins)

– 420 nA Standby mode with RTC

– 1.1 µA Stop 2 mode, 1.4 µA with RTC

– 100 µA/MHz run mode (LDO Mode)

–39 A/MHz run mode (@3.3 V SMPS

Mode)

– Batch acquisition mode (BAM)

– 4 µs wakeup from Stop mode

– Brown out reset (BOR)

– Interconnect matrix

• Core: Arm

32-bit Cortex

-M4 CPU with FPU,

Adaptive real-time accelerator (ART

Accelerator™) allowing 0-wait-state execution

from Flash memory, frequency up to 80 MHz,

MPU, 100DMIPS and DSP instructions

• Performance benchmark

– 1.25 DMIPS/MHz (Drystone 2.1)

– 273.55 CoreMark

(3.42 CoreMark/MHz @

80 MHz)

• Energy benchmark

– 294 ULPMark™ CP score

– 106 ULPMark™ PP score

• Clock Sources

– 4 to 48 MHz crystal oscillator

– 32 kHz crystal oscillator for RTC (LSE)

– Internal 16 MHz factory-trimmed RC (±1%)

– Internal low-power 32 kHz RC (±5%)

– Internal multispeed 100 kHz to 48 MHz

oscillator, auto-trimmed by LSE (better than

±0.25 % accuracy)

– 3 PLLs for system clock, USB, audio, ADC

• Up to 114 fast I/Os, most 5 V-tolerant, up to 14

I/Os with independent supply down to 1.08 V

• RTC with HW calendar, alarms and calibration

• LCD 8× 40 or 4× 44 with step-up converter

• Up to 24 capacitive sensing channels: support

touchkey, linear and rotary touch sensors

• 16x timers: 2x 16-bit advanced motor-control,

2x 32-bit and 5x 16-bit general purpose, 2x 16-

bit basic, 2x low-power 16-bit timers (available

in Stop mode), 2x watchdogs, SysTick timer

• Memories

– Up to 1 MB Flash, 2 banks read-while-

write, proprietary code readout protection

– Up to 128 KB of SRAM including 32 KB

with hardware parity check

– External memory interface for static

memories supporting SRAM, PSRAM,

NOR and NAND memories

– Quad SPI memory interface

• 4x digital filters for sigma delta modulator

• Rich analog peripherals (independent supply)

– 3x 12-bit ADC 5 Msps, up to 16-bit with

hardware oversampling, 200 µA/Msps

– 2x 12-bit DAC output channels, low-power

sample and hold

– 2x operational amplifiers with built-in PGA

– 2x ultra-low-power comparators

• 20x communication interfaces

– USB OTG 2.0 full-speed, LPM and BCD

– 2x SAIs (serial audio interface)

–3x I2C FM+(1 Mbit/s), SMBus/PMBus

– 5x USARTs (ISO 7816, LIN, IrDA, modem)

– 1x LPUART (Stop 2 wake-up)

UFBGA144 (10 × 10)

LQFP144 (20 × 20)

LQFP100 (14

14)

LQFP64 (10 × 10)

UFBGA132 (7 × 7)

WLCSP72

WLCSP81

www.st.com

Downloaded from Arrow.com.

Summary of content (270 pages)

PAGE 1
STM32L476xx Ultra-low-power Arm® Cortex®-M4 32-bit MCU+FPU, 100DMIPS, up to 1MB Flash, 128 KB SRAM, USB OTG FS, LCD, ext. SMPS Datasheet - production data Features • Ultra-low-power with FlexPowerControl – 1.71 V to 3.6 V power supply – -40 °C to 85/105/125 °C temperature range – 300 nA in VBAT mode: supply for RTC and 32x32-bit backup registers – 30 nA Shutdown mode (5 wakeup pins) – 120 nA Standby mode (5 wakeup pins) – 420 nA Standby mode with RTC – 1.1 µA Stop 2 mode, 1.
PAGE 2
STM32L476xx – – – – 3x SPIs (and 1x Quad SPI) CAN (2.0B Active) and SDMMC interface SWPMI single wire protocol master I/F IRTIM (Infrared interface) • 14-channel DMA controller Reference STM32L476xx 2/270 Downloaded from Arrow.com. • True random number generator • CRC calculation unit, 96-bit unique ID • Development support: serial wire debug (SWD), JTAG, Embedded Trace Macrocell™ • All packages are ECOPACK2® compliant Table 1.
PAGE 3
STM32L476xx Contents Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3 Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.1 Arm® Cortex®-M4 core with FPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.
PAGE 4
Contents 4 4/270 Downloaded from Arrow.com. STM32L476xx 3.17 Voltage reference buffer (VREFBUF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 3.18 Comparators (COMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 3.19 Operational amplifier (OPAMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 3.20 Touch sensing controller (TSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 3.
PAGE 5
STM32L476xx Contents 5 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 6 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 6.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112 6.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 6.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . .
PAGE 6
Contents 7 STM32L476xx 6.3.24 VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 6.3.25 LCD controller characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 6.3.26 DFSDM characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 6.3.27 Timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 6.3.28 Communication interfaces characteristics . . . . .
PAGE 7
STM32L476xx List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PAGE 8
List of tables Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. Table 45. Table 46. Table 47. Table 48. Table 49. Table 50. Table 51. Table 52. Table 53. Table 54. Table 55. Table 56. Table 57. Table 58. Table 59. Table 60. Table 61. Table 62. Table 63. Table 64. Table 65. Table 66. Table 67. Table 68. Table 69. Table 70. Table 71. Table 72. Table 73. Table 74. Table 75. Table 76. Table 77. Table 78. Table 79. Table 80. Table 81. 8/270 Downloaded from Arrow.com.
PAGE 9
STM32L476xx Table 82. Table 83. Table 84. Table 85. Table 86. Table 87. Table 88. Table 89. Table 90. Table 91. Table 92. Table 93. Table 94. Table 95. Table 96. Table 97. Table 98. Table 99. Table 100. Table 101. Table 102. Table 103. Table 104. Table 105. Table 106. Table 107. Table 108. Table 109. Table 110. Table 111. Table 112. Table 113. Table 114. Table 115. Table 116. Table 117. Table 118. Table 119. Table 120. Table 121. Table 122. Table 123. Table 124. Table 125. Table 126. Table 127. Table 128.
PAGE 10
List of tables STM32L476xx scale package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255 Table 129. WLCSP72 recommended PCB design rules (0.4 mm pitch BGA) . . . . . . . . . . . . . . . . . . 256 Table 130. LQFP - 64 pins, 10 x 10 mm low-profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258 Table 131. Package thermal characteristics . . . . . . . . . . . . .
PAGE 11
STM32L476xx List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40. Figure 41. Figure 42. Figure 43.
PAGE 12
List of figures Figure 48. Figure 49. Figure 50. Figure 51. Figure 52. Figure 53. Figure 54. Figure 55. Figure 56. Figure 57. Figure 58. Figure 59. Figure 60. Figure 61. Figure 62. Figure 63. Figure 64. Figure 65. Figure 66. Figure 67. Figure 68. Figure 69. Figure 70. Figure 71. Figure 72. Figure 73. Figure 74. Figure 75. Figure 76. Figure 77. Figure 78. 12/270 Downloaded from Arrow.com. STM32L476xx Asynchronous multiplexed PSRAM/NOR write waveforms . . . . . . . . . . . . . . . . . . . . . . .
PAGE 13
STM32L476xx 1 Introduction Introduction This datasheet provides the ordering information and mechanical device characteristics of the STM32L476xx microcontrollers. This document should be read in conjunction with the STM32L4x6 reference manual (RM0351). The reference manual is available from the STMicroelectronics website www.st.com. For information on the Arm®(a) Cortex®-M4 core, please refer to the Cortex®-M4 Technical Reference Manual, available from the www.arm.com website. a.
PAGE 14
Description 2 STM32L476xx Description The STM32L476xx devices are the ultra-low-power microcontrollers based on the highperformance Arm® Cortex®-M4 32-bit RISC core operating at a frequency of up to 80 MHz. The Cortex-M4 core features a Floating point unit (FPU) single precision which supports all Arm® single-precision data-processing instructions and data types. It also implements a full set of DSP instructions and a memory protection unit (MPU) which enhances application security.
PAGE 15
STM32L476xx Description Table 2.
PAGE 16
Description STM32L476xx Table 2. STM32L476xx family device features and peripheral counts (continued) Peripheral STM32 L476Zx STM32 L476Qx STM32 L476Vx Random generator (2) GPIOs Wakeup pins Nb of I/Os down to 1.
PAGE 17
STM32L476xx Description Figure 1.
PAGE 18
Functional overview STM32L476xx 3 Functional overview 3.1 Arm® Cortex®-M4 core with FPU The Arm® Cortex®-M4 with FPU processor is the latest generation of Arm® processors for embedded systems. It was developed to provide a low-cost platform that meets the needs of MCU implementation, with a reduced pin count and low-power consumption, while delivering outstanding computational performance and an advanced response to interrupts.
PAGE 19
STM32L476xx 3.4 Functional overview Embedded Flash memory STM32L476xx devices feature up to 1 Mbyte of embedded Flash memory available for storing programs and data. The Flash memory is divided into two banks allowing readwhile-write operations. This feature allows to perform a read operation from one bank while an erase or program operation is performed to the other bank. The dual bank boot is also supported. Each bank contains 256 pages of 2 Kbyte.
PAGE 20
Functional overview STM32L476xx The whole non-volatile memory embeds the error correction code (ECC) feature supporting: 3.5 • single error detection and correction • double error detection. • The address of the ECC fail can be read in the ECC register Embedded SRAM STM32L476xx devices feature up to 128 Kbyte of embedded SRAM. This SRAM is split into two blocks: • 96 Kbyte mapped at address 0x2000 0000 (SRAM1) • 32 Kbyte located at address 0x1000 0000 with hardware parity check (SRAM2).
PAGE 21
STM32L476xx 3.7 Functional overview Boot modes At startup, BOOT0 pin and BOOT1 option bit are used to select one of three boot options: • Boot from user Flash • Boot from system memory • Boot from embedded SRAM The boot loader is located in system memory. It is used to reprogram the Flash memory by using USART, I2C, SPI, CAN or USB OTG FS in Device mode through DFU (device firmware upgrade). 3.
PAGE 22
Functional overview STM32L476xx Note: If these supplies are tied to ground, the I/Os supplied by these power supplies are not 5 V tolerant (refer to Table 20: Voltage characteristics). Note: VDDIOx is the I/Os general purpose digital functions supply. VDDIOx represents VDDIO1 or VDDIO2, with VDDIO1 = VDD. VDDIO2 supply voltage level is independent from VDDIO1. Figure 2.
PAGE 23
STM32L476xx Functional overview Figure 3. Power-up/down sequence V 3.6 VDDX(1) VDD VBOR0 1 0.3 Power-on Invalid supply area Operating mode VDDX < VDD + 300 mV Power-down VDDX independent from VDD time MSv47490V1 1. VDDX refers to any power supply among VDDA, VDDUSB, VDDIO2, VLCD. 3.9.2 Power supply supervisor The device has an integrated ultra-low-power brown-out reset (BOR) active in all modes except Shutdown and ensuring proper operation after power-on and during power down.
PAGE 24
Functional overview 3.9.3 STM32L476xx Voltage regulator Two embedded linear voltage regulators supply most of the digital circuitries: the main regulator (MR) and the low-power regulator (LPR). • The MR is used in the Run and Sleep modes and in the Stop 0 mode. • The LPR is used in Low-Power Run, Low-Power Sleep, Stop 1 and Stop 2 modes. It is also used to supply the 32 Kbyte SRAM2 in Standby with SRAM2 retention.
PAGE 25
Downloaded from Arrow.com.
PAGE 26
/270 Downloaded from Arrow.com. Stop 1 Stop 0 Mode LPR Range 2(8) Range 1(8) (1) Regulator No No CPU Off Off Flash ON ON SRAM Wakeup source Reset pin, all I/Os BOR, PVD, PVM RTC, LCD, IWDG COMPx (x=1..2) USARTx (x=1...5)(9) LPUART1(9) I2Cx (x=1...3)(10) LPTIMx (x=1,2) OTG_FS(11) SWPMI1(12) Reset pin, all I/Os BOR, PVD, PVM RTC, LCD, IWDG COMPx (x=1..2) USARTx (x=1...5)(9) LPUART1(9) I2Cx (x=1...
PAGE 27
Downloaded from Arrow.com. DS10198 Rev 8 OFF OFF Powered Off Powered Off No CPU Off Off Off Flash Powered Off Powered Off SRAM2 ON ON SRAM Reset pin, all I/Os BOR, PVD, PVM RTC, LCD, IWDG COMPx (x=1..2) I2C3(10) LPUART1(9) LPTIM1 Reset pin 5 I/Os (WKUPx)(13) BOR, RTC, IWDG Reset pin 5 I/Os (WKUPx)(13) RTC BOR, PVD, PVM RTC, LCD, IWDG COMPx (x=1..2) I2C3(10) LPUART1(9) LPTIM1 *** All other peripherals are frozen. BOR, RTC, IWDG *** All other peripherals are powered off.
PAGE 28
/270 Downloaded from Arrow.com. 14. I/Os can be configured with internal pull-up, pull-down or floating in Shutdown mode but the configuration is lost when exiting the Shutdown mode. 13. The I/Os with wakeup from Standby/Shutdown capability are: PA0, PC13, PE6, PA2, PC5. 12. SWPMI1 wakeup by resume from suspend. 11. OTG_FS wakeup by resume from suspend and attach detection protocol event. 10. I2C address detection is functional in Stop mode, and generates a wakeup interrupt in case of address match.
PAGE 29
STM32L476xx Functional overview By default, the microcontroller is in Run mode after a system or a power Reset. It is up to the user to select one of the low-power modes described below: • Sleep mode In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can wake up the CPU when an interrupt/event occurs. • Low-power run mode This mode is achieved with VCORE supplied by the low-power regulator to minimize the regulator's operating current.
PAGE 30
Functional overview • STM32L476xx Shutdown mode The Shutdown mode allows to achieve the lowest power consumption. The internal regulator is switched off so that the VCORE domain is powered off. The PLL, the HSI16, the MSI, the LSI and the HSE oscillators are also switched off. The RTC can remain active (Shutdown mode with RTC, Shutdown mode without RTC). The BOR is not available in Shutdown mode. No power voltage monitoring is possible in this mode, therefore the switch to Backup domain is not supported.
PAGE 31
STM32L476xx Functional overview Table 5.
PAGE 32
Functional overview STM32L476xx Table 5.
PAGE 33
STM32L476xx Functional overview Table 5. Functionalities depending on the working mode(1) (continued) - - O(8) O(8) - - - - - - - - - - - CRC calculation unit O O O O - - - - - - - - - GPIOs O O O O O O O O (9) 5 pins (11) 5 pins - Peripheral Random number generator (RNG) Run Sleep Lowpower run Lowpower sleep - (10) Wakeup capability - Wakeup capability Standby Shutdown Wakeup capability Stop 2 Wakeup capability Stop 0/1 VBAT (10) 1.
PAGE 34
Functional overview 3.10 STM32L476xx Interconnect matrix Several peripherals have direct connections between them. This allows autonomous communication between peripherals, saving CPU resources thus power supply consumption. In addition, these hardware connections allow fast and predictable latency. Depending on peripherals, these interconnections can operate in Run, Sleep, low-power run and sleep, Stop 0, Stop 1 and Stop 2 modes.
PAGE 35
STM32L476xx Functional overview Low-power run Low-power sleep Stop 0 / Stop 1 Stop 2 GPIO Sleep Interconnect source Run Table 6. STM32L476xx peripherals interconnect matrix (continued) TIMx External trigger Y Y Y Y - - LPTIMERx External trigger Y Y Y Y Y (1) ADCx DAC1 DFSDM1 Conversion external trigger Y Y Y Y - - Interconnect destination Interconnect action Y 1. LPTIM1 only. DS10198 Rev 8 35/270 60 Downloaded from Arrow.com.
PAGE 36
Functional overview 3.11 STM32L476xx Clocks and startup The clock controller (see Figure 4) distributes the clocks coming from different oscillators to the core and the peripherals. It also manages clock gating for low-power modes and ensures clock robustness.
PAGE 37
STM32L476xx Functional overview interrupt is generated if enabled. LSE failure can also be detected and generated an interrupt. • Clock-out capability: – MCO: microcontroller clock output: it outputs one of the internal clocks for external use by the application. Low frequency clocks (LSI, LSE) are available down to Stop 1 low power state. – LSCO: low speed clock output: it outputs LSI or LSE in all low-power modes down to Standby mode. LSE can also be output on LSCO in Shutdown mode.
PAGE 38
Functional overview STM32L476xx Figure 4. Clock tree to IWDG LSI RC 32 kHz LSCO to RTC and LCD OSC32_OUT LSE OSC 32.768 kHz /32 OSC32_IN LSE LSI MSI HSE MCO / 1→16 to PWR SYSCLK HSI16 OSC_OUT HSE OSC 4-48 MHz OSC_IN to AHB bus, core, memory and DMA Clock source control PLLCLK AHB PRESC / 1,2,..
PAGE 39
STM32L476xx 3.12 Functional overview General-purpose inputs/outputs (GPIOs) Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the GPIO pins are shared with digital or analog alternate functions. Fast I/O toggling can be achieved thanks to their mapping on the AHB2 bus.
PAGE 40
Functional overview STM32L476xx 3.14 Interrupts and events 3.14.1 Nested vectored interrupt controller (NVIC) The devices embed a nested vectored interrupt controller able to manage 16 priority levels, and handle up to 81 maskable interrupt channels plus the 16 interrupt lines of the Cortex®M4.
PAGE 41
STM32L476xx 3.15 Functional overview Analog to digital converter (ADC) The device embeds 3 successive approximation analog-to-digital converters with the following features: • 12-bit native resolution, with built-in calibration • 5.33 Msps maximum conversion rate with full resolution Down to 18.75 ns sampling time – Increased conversion rate for lower resolution (up to 8.88 Msps for 6-bit resolution) • Up to 24 external channels, some of them shared between ADC1 and ADC2, or ADC1, ADC2 and ADC3.
PAGE 42
Functional overview STM32L476xx To improve the accuracy of the temperature sensor measurement, each device is individually factory-calibrated by ST. The temperature sensor factory calibration data are stored by ST in the system memory area, accessible in read-only mode. Table 8. Temperature sensor calibration values 3.15.2 Calibration value name Description Memory address TS_CAL1 TS ADC raw data acquired at a temperature of 30 °C (± 5 °C), VDDA = VREF+ = 3.
PAGE 43
STM32L476xx Functional overview This digital interface supports the following features: • Up to two DAC output channels • 8-bit or 12-bit output mode • Buffer offset calibration (factory and user trimming) • Left or right data alignment in 12-bit mode • Synchronized update capability • Noise-wave generation • Triangular-wave generation • Dual DAC channel independent or simultaneous conversions • DMA capability for each channel • External triggers for conversion • Sample and hold low-p
PAGE 44
Functional overview 3.18 STM32L476xx Comparators (COMP) The STM32L476xx devices embed two rail-to-rail comparators with programmable reference voltage (internal or external), hysteresis and speed (low speed for low-power) and with selectable output polarity. The reference voltage can be one of the following: • External I/O • DAC output channels • Internal reference voltage or submultiple (1/4, 1/2, 3/4).
PAGE 45
STM32L476xx Functional overview The main features of the touch sensing controller are the following: • Proven and robust surface charge transfer acquisition principle • Supports up to 24 capacitive sensing channels • Up to 3 capacitive sensing channels can be acquired in parallel offering a very good response time • Spread spectrum feature to improve system robustness in noisy environments • Full hardware management of the charge transfer acquisition sequence • Programmable charge transfer freq
PAGE 46
Functional overview STM32L476xx hardware. DFSDM features optional parallel data stream inputs from microcontrollers memory (through DMA/CPU transfers into DFSDM). DFSDM transceivers support several serial interface formats (to support various Σ∆ modulators). DFSDM digital filter modules perform digital processing according user selected filter parameters with up to 24-bit final ADC resolution.
PAGE 47
STM32L476xx Functional overview without having any impact on the timing of “injected” conversions – “injected” conversions for precise timing and with high conversion priority Table 10. DFSDM1 implementation DFSDM features DFSDM1 Number of channels 8 Number of filters 4 Input from internal ADC - Supported trigger sources 3.
PAGE 48
Functional overview STM32L476xx Table 11. Timer feature comparison (continued) Timer type Timer Counter resolution Counter type Prescaler factor DMA request generation Capture/ compare channels Complementary outputs Generalpurpose TIM16, TIM17 16-bit Up Any integer between 1 and 65536 Yes 1 1 Basic TIM6, TIM7 16-bit Up Any integer between 1 and 65536 Yes 0 No 3.24.
PAGE 49
STM32L476xx 3.24.2 Functional overview General-purpose timers (TIM2, TIM3, TIM4, TIM5, TIM15, TIM16, TIM17) There are up to seven synchronizable general-purpose timers embedded in the STM32L476xx (see Table 11 for differences). Each general-purpose timer can be used to generate PWM outputs, or act as a simple time base.
PAGE 50
Functional overview STM32L476xx This low-power timer supports the following features: 3.24.5 • 16-bit up counter with 16-bit autoreload register • 16-bit compare register • Configurable output: pulse, PWM • Continuous/ one shot mode • Selectable software/hardware input trigger • Selectable clock source – Internal clock sources: LSE, LSI, HSI16 or APB clock – External clock source over LPTIM input (working even with no internal clock source running, used by pulse counter application).
PAGE 51
STM32L476xx 3.25 Functional overview Real-time clock (RTC) and backup registers The RTC is an independent BCD timer/counter. It supports the following features: • Calendar with subsecond, seconds, minutes, hours (12 or 24 format), week day, date, month, year, in BCD (binary-coded decimal) format. • Automatic correction for 28, 29 (leap year), 30, and 31 days of the month. • Two programmable alarms. • On-the-fly correction from 1 to 32767 RTC clock pulses.
PAGE 52
Functional overview 3.26 STM32L476xx Inter-integrated circuit interface (I2C) The device embeds three I2C. Refer to Table 12: I2C implementation for the features implementation. The I2C bus interface handles communications between the microcontroller and the serial I2C bus. It controls all I2C bus-specific sequencing, protocol, arbitration and timing. The I2C peripheral supports: • • I2C-bus specification and user manual rev.
PAGE 53
STM32L476xx 3.27 Functional overview Universal synchronous/asynchronous receiver transmitter (USART) The STM32L476xx devices have three embedded universal synchronous receiver transmitters (USART1, USART2 and USART3) and two universal asynchronous receiver transmitters (UART4, UART5). These interfaces provide asynchronous communication, IrDA SIR ENDEC support, multiprocessor communication mode, single-wire half-duplex communication mode and have LIN Master/Slave capability.
PAGE 54
Functional overview 3.28 STM32L476xx Low-power universal asynchronous receiver transmitter (LPUART) The device embeds one Low-Power UART. The LPUART supports asynchronous serial communication with minimum power consumption. It supports half duplex single wire communication and modem operations (CTS/RTS). It allows multiprocessor communication. The LPUART has a clock domain independent from the CPU clock, and can wakeup the system from Stop mode using baudrates up to 220 Kbaud.
PAGE 55
STM32L476xx 3.29 Functional overview Serial peripheral interface (SPI) Three SPI interfaces allow communication up to 40 Mbits/s in master and up to 24 Mbits/s slave modes, in half-duplex, full-duplex and simplex modes. The 3-bit prescaler gives 8 master mode frequencies and the frame size is configurable from 4 bits to 16 bits. The SPI interfaces support NSS pulse mode, TI mode and Hardware CRC calculation. All SPI interfaces can be served by the DMA controller. 3.
PAGE 56
Functional overview STM32L476xx Table 14. SAI implementation SAI features(1) SAI1 SAI2 I2S, LSB or MSB-justified, PCM/DSP, TDM, AC’97 X X Mute mode X X Stereo/Mono audio frame capability. X X 16 slots X X Data size configurable: 8-, 10-, 16-, 20-, 24-, 32-bit X X X (8 Word) X (8 Word) X X FIFO Size SPDIF 1. X: supported 3.
PAGE 57
STM32L476xx Functional overview The CAN peripheral supports: • Supports CAN protocol version 2.0 A, B Active • Bit rates up to 1 Mbit/s • Transmission • • • 3.
PAGE 58
Functional overview STM32L476xx The major features are: • Combined Rx and Tx FIFO size of 1.25 KB with dynamic FIFO sizing • Supports the session request protocol (SRP) and host negotiation protocol (HNP) • 1 bidirectional control endpoint + 5 IN endpoints + 5 OUT endpoints • 12 host channels with periodic OUT support • HNP/SNP/IP inside (no need for any external resistor) • USB 2.0 LPM (Link Power Management) support • Battery Charging Specification Revision 1.
PAGE 59
STM32L476xx 3.36 Functional overview Quad SPI memory interface (QUADSPI) The Quad SPI is a specialized communication interface targeting single, dual or quad SPI flash memories.
PAGE 60
Functional overview STM32L476xx 3.37 Development support 3.37.1 Serial wire JTAG debug port (SWJ-DP) The Arm® SWJ-DP interface is embedded, and is a combined JTAG and serial wire debug port that enables either a serial wire debug or a JTAG probe to be connected to the target.
PAGE 61
STM32L476xx 4 Pinouts and pin description Pinouts and pin description 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 VDD VSS PE1 PE0 PB9 PB8 BOOT0 PB7 PB6 PB5 PB4 (NJTRST) PB3 (JTDO-TRACESWO) PG15 VDDIO2 VSS PG14 PG13 PG12 PG11 PG10 PG9 PD7 PD6 VDD VSS PD5 PD4 PD3 PD2 PD1 PD0 PC12 PC11 PC10 PA15 (JTDI) PA14 (JTCK-SWCLK) Figure 6.
PAGE 62
Pinouts and pin description STM32L476xx 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 VDD VSS VDD12 PE1 PE0 PB9 PB8 BOOT0 PB7 PB6 PB5 PB4 (NJTRST) PB3 (JTDO-TRACESWO) VDDIO2 VSS PG14 PG13 PG12 PG11 PG10 PG9 PD7 PD6 VDD VSS PD5 PD4 PD3 PD2 PD1 PD0 PC12 PC11 PC10 PA15 (JTDI) PA14 (JTCK-SWCLK) Figure 7.
PAGE 63
STM32L476xx Pinouts and pin description Figure 8.
PAGE 64
Pinouts and pin description STM32L476xx Figure 10.
PAGE 65
STM32L476xx Pinouts and pin description Figure 12.
PAGE 66
Pinouts and pin description STM32L476xx Figure 14.
PAGE 67
STM32L476xx Pinouts and pin description VDD VSS VDD12 PB9 PB8 BOOT0 PB7 PB6 PB5 PB4 (NJTRST) PB3 (JTDO-TRACESWO) PC12 PC11 PC10 PA15 (JTDI) PA14 (JTCK-SWCLK) 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 Figure 16.
PAGE 68
Pinouts and pin description STM32L476xx Table 15. Legend/abbreviations used in the pinout table (continued) Name Notes Abbreviation Definition Unless otherwise specified by a note, all I/Os are set as analog inputs during and after reset. Alternate Functions selected through GPIOx_AFR registers functions Pin functions Additional Functions directly selected/enabled through peripheral registers functions 1. The related I/O structures in Table 16 are: FT_f, FT_fa, FT_fl, FT_fla. 2.
PAGE 69
- - - 1 2 - - - 1 2 - - - LQFP64 - LQFP64_SMPS WLCSP72 DS10198 Rev 8 WLCSP72_SMPS - - - - - - - - - - WLCSP81 B8 C7 B8 B9 B9 B9 - - - - - Pin Number 7 6 5 4 3 2 1 LQFP100 Downloaded from Arrow.com.
PAGE 70
- - - - - - - - - - - - - - - - - 4 - 4 3 - 3 LQFP64 - LQFP64_SMPS Downloaded from Arrow.com.
PAGE 71
7 8 9 7 8 9 - 6 - - 6 - - 5 - LQFP64 5 LQFP64_SMPS WLCSP72 WLCSP72_SMPS - - - - - - WLCSP81 DS10198 Rev 8 F8 F9 F8 F9 F8 F9 E9 E9 E9 D8 D8 D8 D9 D9 D9 - - - Pin Number 16 15 14 13 12 - - - LQFP100 Downloaded from Arrow.com.
PAGE 72
Pin Number DS10198 Rev 8 23 14 14 H8 G5 H8 - - - H9 H9 H9 - 13 13 - - 22 21 G8 G8 G8 - - - - 12 12 G9 G9 G9 - 20 - - - - 19 - - - 17 18 F7 WLCSP81 11 11 G7 G7 G7 F7 LQFP64 WLCSP72 10 10 F7 LQFP64_SMPS WLCSP72_SMPS Downloaded from Arrow.com.
PAGE 73
DS10198 Rev 8 27 J9 J8 H8 18 18 19 19 28 29 J8 20 20 G5 H6 G5 J9 26 17 17 H7 H7 H7 J9 25 16 16 G6 G4 G6 24 - 15 15 G4 G6 G4 WLCSP72 - WLCSP72_SMPS - - LQFP64 - WLCSP81 - LQFP64_SMPS Pin Number LQFP100 Downloaded from Arrow.com.
PAGE 74
LQFP64_SMPS LQFP64 Pin Number DS10198 Rev 8 - J6 34 J6 25 - 33 J7 24 24 J7 32 23 23 H4 H4 H4 J7 - 31 - - - - - J8 H5 22 22 H5 30 WLCSP72 21 21 H6 H5 H6 WLCSP72_SMPS WLCSP81 Downloaded from Arrow.com.
PAGE 75
DS10198 Rev 8 J3 - 28 27 - - - - - - - - - - - - - - J4 27 26 J5 LQFP64_SMPS 26 25 LQFP64 WLCSP72 WLCSP72_SMPS - - - - - J6 J5 J4 WLCSP81 - - - - - J3 J4 J5 Pin Number - - - - - 37 36 35 LQFP100 Downloaded from Arrow.com.
PAGE 76
LQFP64_SMPS - - - - - - - - - LQFP64 Downloaded from Arrow.com.
PAGE 77
- - - - - - - - - LQFP64 - LQFP64_SMPS WLCSP72 DS10198 Rev 8 - - - - - WLCSP72_SMPS - - - - - WLCSP81 - - - - - Pin Number 45 44 43 42 41 LQFP100 Downloaded from Arrow.com.
PAGE 78
- LQFP64 - - WLCSP72 WLCSP72_SMPS DS10198 Rev 8 J2 J1 31 31 32 32 F1 J2 B8 J1 J2 - 50 49 - - - 30 48 46 30 29 G3 H3 G3 - Pin Number 47 - WLCSP81 J3 H3 29 28 H3 LQFP64_SMPS Downloaded from Arrow.com.
PAGE 79
LQFP64_SMPS LQFP64 Pin Number 34 34 H2 H2 H2 52 51 WLCSP72 WLCSP81 33 33 H1 H1 H1 WLCSP72_SMPS LQFP100 Downloaded from Arrow.com.
PAGE 80
LQFP64_SMPS LQFP64 Pin Number DS10198 Rev 8 - - F4 56 - - F5 55 - - - - 54 36 36 G1 G1 G1 53 WLCSP72 35 35 G2 G3 G2 WLCSP72_SMPS WLCSP81 Downloaded from Arrow.com.
PAGE 81
- - - - - - - - - - - - - LQFP64 - LQFP64_SMPS WLCSP72 DS10198 Rev 8 - - - - - - - WLCSP72_SMPS - - - - - - - WLCSP81 - - - - - - - Pin Number 61 - - 60 59 58 57 LQFP100 Downloaded from Arrow.com.
PAGE 82
LQFP64_SMPS - - - - - - - - - - LQFP64 Downloaded from Arrow.com.
PAGE 83
LQFP64_SMPS LQFP64 Pin Number DS10198 Rev 8 66 40 40 E1 E1 E1 64 65 F3 39 39 F2 F1 F2 F2 38 38 F1 63 WLCSP72 WLCSP81 37 37 F3 G2 F3 WLCSP72_SMPS LQFP100 Downloaded from Arrow.com.
PAGE 84
LQFP64_SMPS LQFP64 Pin Number 68 69 70 71 72 - 42 42 E3 E3 E3 43 43 D2 D2 D2 44 44 D1 D1 D1 45 45 C1 C1 C1 46 46 C2 C2 C2 47 47 B1 B1 B1 67 WLCSP72 41 41 E2 E2 E2 WLCSP72_SMPS WLCSP81 Downloaded from Arrow.com.
PAGE 85
77 78 51 51 D3 A2 D3 76 49 49 B2 B2 B2 50 50 A2 C3 A2 75 - - - - - - - - 74 Pin Number - LQFP64 - LQFP64_SMPS 73 WLCSP72 WLCSP81 48 48 A1 A1 A1 WLCSP72_SMPS LQFP100 Downloaded from Arrow.com.
PAGE 86
LQFP64_SMPS LQFP64 Pin Number DS10198 Rev 8 - - - 82 - - - 81 - - - - 80 53 53 B3 B3 B3 79 WLCSP72 52 52 C3 D3 C3 WLCSP72_SMPS WLCSP81 Downloaded from Arrow.com.
PAGE 87
- - - - - - - - - - - - 54 - - LQFP64 - LQFP64_SMPS WLCSP81 WLCSP72_SMPS WLCSP72 DS10198 Rev 8 - - - - - - - - - - - - - - D6 D5 E4 - D4 E5 - A3 A3 A3 Pin Number 88 87 - - 86 85 84 83 LQFP100 Downloaded from Arrow.com.
PAGE 88
- - - - - - - - - - - - - - - LQFP64 - LQFP64_SMPS Downloaded from Arrow.com.
PAGE 89
DS10198 Rev 8 90 91 56 55 C6 C5 C6 57 56 C7 E7 C7 89 - 55 54 A6 A6 A6 WLCSP72 - WLCSP72_SMPS - - LQFP64 - WLCSP81 - LQFP64_SMPS Pin Number LQFP100 Downloaded from Arrow.com.
PAGE 90
LQFP64_SMPS LQFP64 Pin Number DS10198 Rev 8 93 94 95 59 58 A7 B7 A7 60 59 D7 A7 D7 61 60 E7 C6 E7 92 WLCSP72 58 57 B7 E8 B7 WLCSP72_SMPS WLCSP81 Downloaded from Arrow.com.
PAGE 91
LQFP64_SMPS LQFP64 Pin Number DS10198 Rev 8 UFBGA132_SMPS C4 D3 C6 A2 C3 B3 LQFP144_SMPS LQFP144 142 - B4 A2 C4 UFBGA144 144 144 - 143 143 M1 - 142 141 141 140 140 139 VDD VSS VDD12 PE1 PE0 PB9 Pin name (function after reset) Pin type S S S I/O I/O I/O I/O structure - - - FT_l FT_l FT_fl - - - - - - Notes - - - - - - LCD_SEG37, FMC_NBL1, TIM17_CH1, EVENTOUT - - - Additional functions TIM4_ETR, LCD_SEG36, FMC_NBL0, TIM16_CH1, EVENTOUT IR_OUT, TIM4_C
PAGE 92
/270 Downloaded from Arrow.com.
PAGE 93
Downloaded from Arrow.com.
PAGE 94
/270 Downloaded from Arrow.com.
PAGE 95
Downloaded from Arrow.com.
PAGE 96
/270 Downloaded from Arrow.com.
PAGE 97
Downloaded from Arrow.com.
PAGE 98
/270 Downloaded from Arrow.com. DS10198 Rev 8 - - - - - - - - - - PG8 PG9 PG10 PG11 PG12 PG13 PG14 PG15 PH0 PH1 - PG5 - - LPTIM1_OUT - - LPTIM1_ETR LPTIM1_IN2 LPTIM1_IN1 - - - - - - - - - - - - - - - - - - - - - - - - - - - TIM1/TIM2/ TIM3/TIM4/ TIM5 TIM1/TIM2/ TIM5/TIM8/ LPTIM1 - AF2 AF1 1. Please refer to Table 18 for AF8 to AF15.
PAGE 99
Downloaded from Arrow.com.
PAGE 100
/270 Downloaded from Arrow.com.
PAGE 101
Downloaded from Arrow.com.
PAGE 102
/270 Downloaded from Arrow.com.
PAGE 103
Downloaded from Arrow.com.
PAGE 104
/270 Downloaded from Arrow.com.
PAGE 105
Downloaded from Arrow.com.
PAGE 106
/270 Downloaded from Arrow.com. - - PH0 PH1 - - CAN1, TSC UART4, UART5, LPUART1 1. Please refer to Table 17 for AF0 to AF7. Port H Port AF9 AF8 - - OTG_FS, QUADSPI AF10 - - LCD AF11 - - SDMMC1, COMP1, COMP2, FMC, SWPMI1 AF12 Table 18.
PAGE 107
STM32L476xx 5 Memory mapping Memory mapping Figure 17.
PAGE 108
Memory mapping STM32L476xx Table 19. STM32L476xx memory map and peripheral register boundary addresses(1) Bus AHB3 AHB2 - AHB1 108/270 Downloaded from Arrow.com.
PAGE 109
STM32L476xx Memory mapping Table 19.
PAGE 110
Memory mapping STM32L476xx Table 19. STM32L476xx memory map and peripheral register boundary addresses(1) (continued) Bus APB1 110/270 Downloaded from Arrow.com.
PAGE 111
STM32L476xx Memory mapping Table 19.
PAGE 112
Electrical characteristics STM32L476xx 6 Electrical characteristics 6.1 Parameter conditions Unless otherwise specified, all voltages are referenced to VSS. 6.1.1 Minimum and maximum values Unless otherwise specified, the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at TA = 25 °C and TA = TAmax (given by the selected temperature range).
PAGE 113
STM32L476xx 6.1.6 Electrical characteristics Power supply scheme Figure 20. Power supply scheme VBAT VBAT 1.55 – 3.6 V 1.55 – 3.6 V Backup circuitry Backup circuitry (LSE, RTC, (LSE, RTC, Backup registers) Backup registers) Backup circuitry (LSE, RTC, Backup registers) VVCORE CORE VBAT Power switch Power switch 1.55 – 3.6 V VVDD DD Power switch nnx xVDD VDD Regulator Regulator 2 x VDD12 OUT OUT nnxx100 100nF nF GPIOs GPIOs +1xx4.7 4.
PAGE 114
Electrical characteristics STM32L476xx below, the appropriate pins on the underside of the PCB to ensure the good functionality of the device. 114/270 Downloaded from Arrow.com.
PAGE 115
STM32L476xx 6.1.7 Electrical characteristics Current consumption measurement Figure 21. Current consumption measurement scheme with and without external SMPS power supply IDD_USB IDD_USB VDDUSB VDDUSB IDD_VBAT IDD_VBAT VBAT VBAT IDD IDD IDDA SMPS VDD12 VDD VDD VDDIO2 VDDIO2 IDDA VDDA VDDA MSv45730V1 6.
PAGE 116
Electrical characteristics STM32L476xx Table 20. Voltage characteristics(1) (continued) Symbol |∆VDDx| |VSSx-VSS| Ratings Min Max Unit Variations between different VDDX power pins of the same domain - 50 mV Variations between all the different ground pins(5) - 50 mV 1. All main power (VDD, VDDA, VDDIO2, VDDUSB, VLCD, VBAT) and ground (VSS, VSSA) pins must always be connected to the external power supply, in the permitted range. 2. VIN maximum must always be respected.
PAGE 117
STM32L476xx Electrical characteristics Table 22. Thermal characteristics Symbol TSTG TJ Ratings Storage temperature range Maximum junction temperature DS10198 Rev 8 Value Unit –65 to +150 °C 150 °C 117/270 238 Downloaded from Arrow.com.
PAGE 118
Electrical characteristics STM32L476xx 6.3 Operating conditions 6.3.1 General operating conditions Table 23. General operating conditions Symbol Parameter Conditions Min Max fHCLK Internal AHB clock frequency - 0 80 fPCLK1 Internal APB1 clock frequency - 0 80 fPCLK2 Internal APB2 clock frequency - 0 80 VDD Standard operating voltage - VDD12 Standard operating voltage VDDIO2 PG[15:2] I/Os supply voltage VDDA Analog supply voltage 1.
PAGE 119
STM32L476xx Electrical characteristics Table 23.
PAGE 120
Electrical characteristics STM32L476xx Table 24. Operating conditions at power-up / power-down(1) (continued) Symbol Parameter Conditions VDDIO2 rise time rate tVDDIO2 Min Max 0 ∞ 10 ∞ - VDDIO2 fall time rate Unit µs/V 1. At power-up, the VDD12 voltage should not be forced externally. The requirements for power-up/down sequence specified in Section 3.9.1: Power supply schemes must be respected. 6.3.
PAGE 121
STM32L476xx Electrical characteristics Table 25. Embedded reset and power control block characteristics (continued) Conditions(1) Min Typ Max Rising edge 2.92 2.98 3.04 Falling edge 2.84 2.90 2.
PAGE 122
Electrical characteristics 6.3.4 STM32L476xx Embedded voltage reference The parameters given in Table 26 are derived from tests performed under the ambient temperature and supply voltage conditions summarized in Table 23: General operating conditions. Table 26. Embedded internal voltage reference Symbol VREFINT Parameter Internal reference voltage Conditions –40 °C < TA < +130 °C Min Typ Max Unit 1.182 1.212 1.
PAGE 123
STM32L476xx Electrical characteristics Figure 22. VREFINT versus temperature V 1.235 1.23 1.225 1.22 1.215 1.21 1.205 1.2 1.195 1.19 1.185 -40 -20 0 20 40 Mean 60 Min 80 100 120 °C Max MSv40169V1 DS10198 Rev 8 123/270 238 Downloaded from Arrow.com.
PAGE 124
Electrical characteristics 6.3.5 STM32L476xx Supply current characteristics The current consumption is a function of several parameters and factors such as the operating voltage, ambient temperature, I/O pin loading, device software configuration, operating frequencies, I/O pin switching rate, program location in memory and executed binary code. The current consumption is measured as described in Figure 21: Current consumption measurement scheme with and without external SMPS power supply.
PAGE 125
Downloaded from Arrow.com. Supply current in fHCLK = fMSI Low-power all peripherals disable run mode IDD_ALL (Run) IDD_ALL (LPRun) DS10198 Rev 8 8.25 6.28 4.24 3.21 2.19 272 154 78 42 64 MHz Range 1 48 MHz 32 MHz 24 MHz 16 MHz 2 MHz 1 MHz 400 kHz 100 kHz 1. Guaranteed by characterization results, unless otherwise specified. 9.24 72 MHz 0.14 100 kHz 10.2 0.23 1 MHz 0.34 2 MHz 0.98 8 MHz 0.55 1.83 16 MHz 4 MHz 2.88 26 MHz 73 108 184 303 2.24 3.27 4.30 6.35 8.32 9.31 10.3 0.
PAGE 126
/270 Downloaded from Arrow.com. DS10198 Rev 8 Supply current in Run mode IDD_ALL(Run) fHCLK = fHSE up to 48MHz included, bypass mode PLL ON above 48 MHz all peripherals disable - Conditions(1) 0.10 0.06 100 kHz 0.79 16 MHz 1 MHz 1.15 24 MHz 0.15 1.52 32 MHz 2 MHz 2.26 48 MHz 0.24 2.97 64 MHz 4 MHz 3.32 72 MHz 0.42 3.67 80 MHz 8 MHz 25 °C fHCLK 0.07 0.11 0.16 0.25 0.44 0.81 1.18 1.55 2.28 2.99 3.35 3.70 55 °C 0.12 0.16 0.20 0.30 0.48 0.85 1.22 1.60 2.
PAGE 127
Downloaded from Arrow.com. Supply current in fHCLK = fMSI Low-power all peripherals disable run IDD_ALL (Run) IDD_ALL (LPRun) DS10198 Rev 8 4.16 2.93 358 197 97 47 24 MHz 16 MHz 2 MHz 1 MHz 400 kHz 100 kHz 1. Guaranteed by characterization results, unless otherwise specified. 7.64 5.49 32 MHz 9.06 10.0 80 MHz 8.96 0.14 100 kHz 64 MHz 0.27 1 MHz 72 MHz 0.42 2 MHz 1.26 8 MHz 0.71 2.24 16 MHz 4 MHz 3.15 26 MHz 77 126 230 392 2.99 4.22 5.57 7.72 9.04 9.13 10.1 0.17 0.30 0.
PAGE 128
/270 Downloaded from Arrow.com. DS10198 Rev 8 Supply current in Run mode IDD_ALL(Run) fHCLK = fHSE up to 48MHz included, bypass mode PLL ON above 48 MHz all peripherals disable - Conditions(1) 25 °C 3.59 3.26 3.22 2.75 1.97 1.50 1.05 0.54 0.31 0.18 0.12 0.06 fHCLK 80 MHz 72 MHz 64 MHz 48 MHz 32 MHz 24 MHz 16 MHz 8 MHz 4 MHz 2 MHz 1 MHz 100 kHz 0.07 0.13 0.19 0.32 0.56 1.07 1.52 2.00 2.78 3.25 3.28 3.63 55 °C 0.12 0.17 0.24 0.37 0.60 1.13 1.57 2.06 2.84 3.31 3.34 3.
PAGE 129
Downloaded from Arrow.com. fHCLK = fMSI all peripherals disable FLASH in power-down Supply current in low-power run mode DS10198 Rev 8 Range 1 61 26 100 kHz 242 2 MHz 400 kHz 2.18 16 MHz 130 3.20 1 MHz 4.22 24 MHz 8.25 64 MHz 32 MHz 9.25 72 MHz 6.26 10.2 80 MHz 48 MHz 0.22 0.12 1 MHz 100 kHz 0.33 2 MHz 0.97 0.54 8 MHz 4 MHz 2.88 1.83 26 MHz 16 MHz 25 °C fHCLK 1. Guaranteed by characterization results, unless otherwise specified.
PAGE 130
/270 Downloaded from Arrow.com. Parameter DS10198 Rev 8 fHCLK = fHSE up to 48MHz included, bypass mode PLL ON above 48 MHz all peripherals disable - Conditions(1) 3.67 3.33 2.97 2.25 1.52 1.15 0.78 0.42 0.23 0.14 0.09 0.05 80 MHz 72 MHz 64 MHz 48 MHz 32 MHz 24 MHz 16 MHz 8 MHz 4 MHz 2 MHz 1 MHz 100 kHz 0.06 0.11 0.16 0.25 0.43 0.80 1.17 1.54 2.28 2.99 3.35 3.70 25 °C 55 °C fHCLK 0.11 0.15 0.20 0.29 0.48 0.84 1.22 1.59 2.33 3.04 3.40 3.77 85 °C TYP 0.18 0.22 0.27 0.
PAGE 131
STM32L476xx Electrical characteristics Table 33. Typical current consumption in Run and Low-power run modes, with different codes running from Flash, ART enable (Cache ON Prefetch OFF) Conditions Parameter Supply current in Run mode Range 2 fHCLK = 26 MHz IDD_ALL (Run) fHCLK = fHSE up to 48 MHz included, bypass mode PLL ON above 48 MHz all peripherals disable Code 25 °C Reduced code(1) 2.9 111 Coremark 3.1 118 Dhrystone 2.1 3.1 Fibonacci 2.9 112 2.8 108 Reduced code 10.
PAGE 132
Electrical characteristics STM32L476xx 1. All values are obtained by calculation based on measurements done without SMPS and using following parameters: SMPS input = 3.3 V, SMPS efficiency = 85%, VDD12 = 1.10 V 2. Reduced code used for characterization results provided in Table 27, Table 29, Table 31. Table 35. Typical current consumption in Run, with different codes running from Flash, ART enable (Cache ON Prefetch OFF) and power supplied by external SMPS (VDD12 = 1.
PAGE 133
STM32L476xx Electrical characteristics Table 37. Typical current consumption in Run modes, with different codes running from Flash, ART disable and power supplied by external SMPS (VDD12 = 1.10 V) Conditions(1) IDD_ALL (Run) Parameter Supply current in Run mode Voltage scaling - fHCLK = fHSE up to 48 MHz included, bypass mode PLL ON above 48 MHz all peripherals disable fHCLK = 80 MHz fHCLK = 26 MHz Symbol TYP Code 25 °C Reduced code(2) 1.34 TYP Unit Unit 25 °C 51 Coremark 1.
PAGE 134
Electrical characteristics STM32L476xx Table 39.
PAGE 135
STM32L476xx Electrical characteristics Table 41. Typical current consumption in Run mode, with different codes running from SRAM1 and power supplied by external SMPS (VDD12 = 1.05 V) Conditions(1) IDD_ALL (Run) Parameter Supply current in Run mode fHCLK = fHSE up to 48 MHz included, bypass mode PLL ON above 48 MHz all peripherals disable Voltage scaling fHCLK = 26 MHz Symbol TYP TYP Unit Code 25 °C Reduced code(2) 1.14 44 Coremark 1.14 44 Dhrystone 2.1 1.14 Fibonacci 1.
PAGE 136
/270 Downloaded from Arrow.com. DS10198 Rev 8 IDD_ALL (Sleep) 0.18 0.15 0.12 2.96 2.69 2.41 1.88 1.30 1.01 0.71 96 65 43 33 1 MHz 100 kHz 80 MHz 72 MHz 64 MHz Range 1 48 MHz 32 MHz 24 MHz 16 MHz 2 MHz 1 MHz 400 kHz 100 kHz 8 MHz 2 MHz 0.61 0.36 16 MHz 0.24 0.92 26 MHz 63 73 94 126 0.75 1.05 1.35 1.93 2.45 2.73 3.00 0.14 0.17 0.20 0.27 0.40 0.65 0.96 25 °C 55 °C fHCLK 4 MHz Range 2 Voltage scaling 1. Guaranteed by characterization results, unless otherwise specified.
PAGE 137
Downloaded from Arrow.com. Supply current in sleep mode, IDD_ALL(Sleep) fHCLK = fHSE up to 48 MHz included, bypass mode PLL ON above 48 MHz all peripherals disable - Conditions(1) 25 °C 1.06 0.97 0.87 0.68 0.47 0.36 0.26 0.16 0.10 0.08 0.06 0.05 fHCLK 80 MHz 72 MHz 64 MHz 48 MHz 32 MHz 24 MHz 16 MHz 8 MHz 4 MHz 2 MHz 1 MHz 100 kHz 0.06 0.07 0.09 0.12 0.17 0.27 0.38 0.49 0.69 0.88 0.98 1.08 55 °C 0.10 0.12 0.13 0.16 0.22 0.31 0.42 0.53 0.74 0.93 1.02 1.13 85 °C TYP 0.18 0.
PAGE 138
/270 Downloaded from Arrow.com. IDD_ALL (Stop 2) Supply current in Stop 2 mode, RTC enabled Supply current in Stop 2 mode, RTC disabled IDD_ALL (Stop 2 with RTC) Parameter Symbol DS10198 Rev 8 4.9 2.04 1.43 1.54 1.67 1.87 1.8 V 2.4 V 3V 3.6 V 4.57 4.29 4.11 3.99 4.55 RTC clocked by LSE quartz(4) in low drive mode, LCD disabled 4.33 1.79 4.13 4.65 4.43 4.32 4.07 4.65 4.37 4.22 4.04 4.47 4.24 4.07 3.98 4.11 3.97 3.86 1.63 1.5 1.8 V 1.69 3V 1.86 1.62 2.4 V 3.6 V 1.
PAGE 139
Downloaded from Arrow.com. Parameter 3V 3V 3V Wakeup clock is MSI = 4 MHz, voltage Range 2. See (5). Wakeup clock is HSI16 = 16 MHz, voltage Range 1. See (5). VDD Wakeup clock is MSI = 48 MHz, voltage Range 1. See (5). - Conditions 2.1 2.24 1.9 - - - 25 °C 55 °C - - - 85 °C TYP - - - - - - 105 °C 125 °C 25 °C 55 °C 5. Wakeup with code execution from Flash. Average value given for a typical wakeup time as specified in Table 52: Low-power mode wakeup timings.
PAGE 140
/270 Downloaded from Arrow.com. Supply current in Stop 1 mode, RTC disabled IDD_ALL (Stop 1) RTC clocked by LSI - - - DS10198 Rev 8 RTC clocked by LSE quartz(3) in low drive mode LCD disabled LCD disabled LCD enabled(2) LCD disabled LCD enabled(2) clocked by LSI LCD disabled - Conditions Supply current IDD_ALL in stop 1 (Stop 1 with mode, RTC) RTC enabled RTC clocked by LSE bypassed at 32768 Hz Parameter Symbol 25.3 25.7 7.14 7.31 7.41 6.91 7.04 2.4 V 3V 3.6 V 1.8 V 2.4 V 25.7 25.
PAGE 141
Downloaded from Arrow.com. Parameter - Wakeup clock MSI = 48 MHz, voltage Range 1. See (4). - Conditions MAX(1) 1.7 1.62 3V 1.47 - - - - - - - - - - - - 4. Wakeup with code execution from Flash. Average value given for a typical wakeup time as specified in Table 52: Low-power mode wakeup timings. 3. Based on characterization done with a 32.768 kHz crystal (MC306-G-06Q-32.768, manufacturer JFVNY) with two 6.8 pF loading capacitors.
PAGE 142
/270 Downloaded from Arrow.com. Supply current in Stop 0 mode, RTC disabled IDD_ALL (Stop 0) 108 110 111 113 1.8 V 2.4 V 3V 3.6 V 2. Guaranteed by test in production. 137 135 134 132 25 °C 55 °C VDD Conditions 1. Guaranteed by characterization results, unless otherwise specified. Parameter Symbol 222 220 219 217 85 °C TYP 363 360 358 356 642 637 634 631 166 161 158 153 105 °C 125 °C 25 °C Table 47.
PAGE 143
Downloaded from Arrow.com. IDD_ALL (Standby) IDD_ALL (Standby with RTC) Supply current in Standby mode (backup registers retained), RTC disabled Supply current in Standby mode (backup registers retained), RTC enabled Parameter Symbol DS10198 Rev 8 114 138 1.8 V 2.4 V - 198 317 391 3.6 V 1.8 V 2.4 V - 671 853 396 2.4 V 796 961 416 514 652 821 1.8 V 2.4 V RTC clocked by LSE quartz (3) in low drive mode 3 V 3.6 V 1226 640 1111 528 710 3V 527 289 - 1.8 V 663 3V - 885 557 2.
PAGE 144
/270 Downloaded from Arrow.com. Supply current to be added in Standby mode when SRAM2 is retained Supply current during wakeup from Standby mode Parameter Wakeup clock is MSI = 4 MHz. See (5). - - Conditions 236 235 3V 3.
PAGE 145
Downloaded from Arrow.com. Supply current in Shutdown mode (backup registers retained) RTC enabled IDD_ALL (Shutdown with RTC) Wakeup clock is MSI = 4 MHz. See (3). RTC clocked by LSE quartz (2) in low drive mode RTC clocked by LSE bypassed at 32768 Hz - Conditions 729 3.
PAGE 146
/270 Downloaded from Arrow.com. RTC disabled - Conditions RTC enabled and clocked by LSE quartz(2) RTC enabled and Backup domain clocked by LSE supply current bypassed at 32768 Hz Parameter 494 630 3V 3.6 V 388 302 1.8 V 2.4 V 508 3.6 V 183 1.8 V 376 10 3.6 V 268 6 3V 3V 5.27 2.4 V 2.
PAGE 147
STM32L476xx Electrical characteristics I/O system current consumption The current consumption of the I/O system has two components: static and dynamic. I/O static current consumption All the I/Os used as inputs with pull-up generate current consumption when the pin is externally held low. The value of this current consumption can be simply computed by using the pull-up/pull-down resistors values given in Table 70: I/O static characteristics.
PAGE 148
Electrical characteristics STM32L476xx On-chip peripheral current consumption The current consumption of the on-chip peripherals is given in Table 51.
PAGE 149
STM32L476xx Electrical characteristics Table 51. Peripheral current consumption (continued) Range 1 Range 2 Low-power run and sleep SRAM2 1.6 1.4 1.6 TSC 1.8 1.4 1.6 118.5 77.3 87.6 AHB to APB1 bridge 0.9 0.7 0.9 CAN1 4.6 4.0 4.4 DAC1 2.4 1.9 2.2 I2C1 independent clock domain 3.7 3.1 3.2 I2C1 APB clock domain 1.3 1.1 1.5 I2C2 independent clock domain 3.7 3.0 3.2 I2C2 APB clock domain 1.4 1.1 1.5 I2C3 independent clock domain 2.9 2.3 2.
PAGE 150
Electrical characteristics STM32L476xx Table 51. Peripheral current consumption (continued) Range 1 Range 2 Low-power run and sleep USART2 independent clock domain 4.1 3.6 3.8 USART2 APB clock domain 1.4 1.1 1.5 USART3 independent clock domain 4.7 4.1 4.2 USART3 APB clock domain 1.5 1.3 1.7 UART4 independent clock domain 3.9 3.2 3.5 UART4 APB clock domain 1.5 1.3 1.6 UART5 independent clock domain 3.9 3.2 3.5 UART5 APB clock domain 1.3 1.2 1.4 WWDG 0.5 0.5 0.
PAGE 151
STM32L476xx Electrical characteristics 1. The BusMatrix is automatically active when at least one master is ON (CPU, DMA). 2. The GPIOx (x= A…H) dynamic current consumption is approximately divided by a factor two versus this table values when the GPIO port is locked thanks to LCKK and LCKy bits in the GPIOx_LCKR register.
PAGE 152
Electrical characteristics STM32L476xx Table 52.
PAGE 153
STM32L476xx Electrical characteristics Table 53. Regulator modes transition times(1) Symbol Parameter tWULPRUN tVOST Conditions Typ Max Wakeup time from Low-power run mode to Code run with MSI 2 MHz Run mode(2) 5 7 Regulator transition time from Range 2 to Range 1 or Range 1 to Range 2(3) 20 40 Typ Max Stop 0 mode - 1.7 Stop 1 mode and Stop 2 mode - 8.5 Unit µs Code run with MSI 24 MHz 1. Guaranteed by characterization results. 2. Time until REGLPF flag is cleared in PWR_SR2. 3.
PAGE 154
Electrical characteristics STM32L476xx Figure 23. High-speed external clock source AC timing diagram tw(HSEH) VHSEH 90% 10% VHSEL tr(HSE) tf(HSE) t tw(HSEL) THSE MS19214V2 Low-speed external user clock generated from an external source In bypass mode the LSE oscillator is switched off and the input pin is a standard GPIO. The external clock signal has to respect the I/O characteristics in Section 6.3.14. However, the recommended clock input waveform is shown in Figure 24. Table 56.
PAGE 155
STM32L476xx Electrical characteristics High-speed external clock generated from a crystal/ceramic resonator The high-speed external (HSE) clock can be supplied with a 4 to 48 MHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on design simulation results obtained with typical external components specified in Table 57.
PAGE 156
Electrical characteristics Note: STM32L476xx For information on selecting the crystal, refer to the application note AN2867 “Oscillator design guide for ST microcontrollers” available from the ST website www.st.com. Figure 25. Typical application with an 8 MHz crystal Resonator with integrated capacitors CL1 OSC_IN 8 MHz resonator CL2 REXT (1) fHSE RF Bias controlled gain OSC_OUT MS19876V1 1. REXT value depends on the crystal characteristics.
PAGE 157
STM32L476xx Electrical characteristics 1. Guaranteed by design. 2. Refer to the note and caution paragraphs below the table, and to the application note AN2867 “Oscillator design guide for ST microcontrollers”. 3. tSU(LSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 32.768 kHz oscillation is reached.
PAGE 158
Electrical characteristics 6.3.8 STM32L476xx Internal clock source characteristics The parameters given in Table 59 are derived from tests performed under ambient temperature and supply voltage conditions summarized in Table 23: General operating conditions. The provided curves are characterization results, not tested in production. High-speed internal (HSI16) RC oscillator Table 59.
PAGE 159
STM32L476xx Electrical characteristics Figure 27. HSI16 frequency versus temperature MHz 16.4 +2 % 16.3 +1.5 % 16.2 +1 % 16.1 16 15.9 -1 % 15.8 -1.5 % 15.7 -2 % 15.6 -40 -20 0 Mean 20 40 60 min 80 100 120 °C max MSv39299V2 DS10198 Rev 8 159/270 238 Downloaded from Arrow.com.
PAGE 160
Electrical characteristics STM32L476xx Multi-speed internal (MSI) RC oscillator Table 60. MSI oscillator characteristics(1) Symbol Parameter Conditions Min Typ Max Range 0 99 100 101 Range 1 198 200 202 Range 2 396 400 404 Range 3 792 800 808 Range 4 0.99 1 1.01 Range 5 1.98 2 2.02 Range 6 3.96 4 4.04 Range 7 7.92 8 8.08 Range 8 15.8 16 16.16 Range 9 23.8 24 24.4 Range 10 31.7 32 32.32 Range 11 47.5 48 48.48 Range 0 - 98.304 - Range 1 - 196.
PAGE 161
STM32L476xx Electrical characteristics Table 60. MSI oscillator characteristics(1) (continued) Symbol Parameter Conditions Min Typ VDD=1.62 V to 3.6 V -1.2 - VDD=2.4 V to 3.6 V -0.5 - VDD=1.62 V to 3.6 V -2.5 - VDD=2.4 V to 3.6 V -0.8 - VDD=1.62 V to 3.6 V -5 - VDD=2.4 V to 3.6 V -1.
PAGE 162
Electrical characteristics STM32L476xx Table 60. MSI oscillator characteristics(1) (continued) Symbol IDD(MSI)(6) Parameter MSI oscillator power consumption Conditions MSI and PLL mode Min Typ Max Range 0 - - 0.6 1 Range 1 - - 0.8 1.2 Range 2 - - 1.2 1.7 Range 3 - - 1.9 2.5 Range 4 - - 4.7 6 Range 5 - - 6.5 9 Range 6 - - 11 15 Range 7 - - 18.5 25 Range 8 - - 62 80 Range 9 - - 85 110 Range 10 - - 110 130 Range 11 - - 155 190 Unit µA 1.
PAGE 163
STM32L476xx Electrical characteristics Figure 28. Typical current consumption versus MSI frequency Low-speed internal (LSI) RC oscillator Table 61. LSI oscillator characteristics(1) Symbol fLSI tSU(LSI)(2) tSTAB(LSI)(2) IDD(LSI)(2) Parameter LSI Frequency Conditions Min Typ Max VDD = 3.0 V, TA = 30 °C 31.04 - 32.96 VDD = 1.62 to 3.6 V, TA = -40 to 125 °C 29.
PAGE 164
Electrical characteristics STM32L476xx Table 62. PLL, PLLSAI1, PLLSAI2 characteristics(1) Symbol fPLL_IN Parameter Conditions Min Typ Max Unit PLL input clock(2) - 4 - 16 MHz PLL input clock duty cycle - 45 - 55 % Voltage scaling Range 1 2.0645 - 80 Voltage scaling Range 2 2.
PAGE 165
STM32L476xx Electrical characteristics Table 63. Flash memory characteristics(1) (continued) Symbol IDD Parameter Conditions Average consumption from VDD Maximum current (peak) Typ Max Write mode 3.4 - Erase mode 3.4 - Write mode 7 (for 2 μs) - Erase mode 7 (for 41 μs) - Unit mA 1. Guaranteed by design. Table 64.
PAGE 166
Electrical characteristics 6.3.11 STM32L476xx EMC characteristics Susceptibility tests are performed on a sample basis during device characterization. Functional EMS (electromagnetic susceptibility) While a simple application is executed on the device (toggling 2 LEDs through I/O ports). the device is stressed by two electromagnetic events until a failure occurs.
PAGE 167
STM32L476xx Electrical characteristics Prequalification trials Most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1 second. To complete these trials, ESD stress can be applied directly on the device, over the range of specification values. When unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note AN1015).
PAGE 168
Electrical characteristics STM32L476xx Static latch-up Two complementary static tests are required on six parts to assess the latch-up performance: • A supply overvoltage is applied to each power supply pin. • A current injection is applied to each input, output and configurable I/O pin. These tests are compliant with EIA/JESD 78A IC latch-up standard. Table 68. Electrical sensitivities Symbol LU Parameter Static latch-up class Conditions Class TA = +105 °C conforming to JESD78A II level A(1) 1.
PAGE 169
STM32L476xx 6.3.14 Electrical characteristics I/O port characteristics General input/output characteristics Unless otherwise specified, the parameters given in Table 70 are derived from tests performed under the conditions summarized in Table 23: General operating conditions. All I/Os are designed as CMOS- and TTL-compliant (except BOOT0). Table 70. I/O static characteristics Symbol VIL(1) VIH (1) Parameter Conditions Typ Max Unit I/O input low level voltage except BOOT0 1.62 V
PAGE 170
Electrical characteristics STM32L476xx Table 70. I/O static characteristics (continued) Symbol Parameter FT_xx input leakage current(3)(5) Conditions Min Typ Max VIN ≤ Max(VDDXXX)(6)(7) - - ±100 Max(VDDXXX) ≤ VIN ≤ Max(VDDXXX)+1 V(6)(7) - - 650 Max(VDDXXX)+1 V < VIN ≤ 5.5 V(6)(7) - - 200 - - ±150 - - 2500(3) VIN ≤ Max(VDDXXX) (6)(7) Ilkg(4) FT_lu, FT_u and PC3 Max(VDDXXX) ≤ VIN ≤ I/Os Max(VDDXXX)+1 V(6)(7) TT_xx input leakage current nA Max(VDDXXX)+1 V < VIN ≤ 5.
PAGE 171
STM32L476xx Electrical characteristics All I/Os are CMOS- and TTL-compliant (no software configuration required). Their characteristics cover more than the strict CMOS-technology or TTL parameters. The coverage of these requirements is shown in Figure 29 for standard I/Os, and in Figure 29 for 5 V tolerant I/Os. Figure 29. I/O input characteristics TTL requirement Vih min = 2V x V DDIO di este n pr odu T Base Bas d u on sim lation simu ed on T cti M on C OS ire requ .
PAGE 172
Electrical characteristics STM32L476xx Output voltage levels Unless otherwise specified, the parameters given in the table below are derived from tests performed under the ambient temperature and supply voltage conditions summarized in Table 23: General operating conditions. All I/Os are CMOS- and TTL-compliant (FT OR TT unless otherwise specified). Table 71. Output voltage characteristics(1) Symbol VOL VOH Parameter Conditions Min Max - 0.4 VDDIOx-0.4 - - 0.4 2.4 - - 1.3 VDDIOx-1.
PAGE 173
STM32L476xx Electrical characteristics Table 72. I/O AC characteristics(1)(2) Speed Symbol Fmax Parameter Maximum frequency 00 Tr/Tf Fmax Output rise and fall time Maximum frequency 01 Tr/Tf Output rise and fall time Conditions Min Max C=50 pF, 2.7 V≤VDDIOx≤3.6 V - 5 C=50 pF, 1.62 V≤VDDIOx≤2.7 V - 1 C=50 pF, 1.08 V≤VDDIOx≤1.62 V - 0.1 C=10 pF, 2.7 V≤VDDIOx≤3.6 V - 10 C=10 pF, 1.62 V≤VDDIOx≤2.7 V - 1.5 C=10 pF, 1.08 V≤VDDIOx≤1.62 V - 0.1 C=50 pF, 2.7 V≤VDDIOx≤3.
PAGE 174
Electrical characteristics STM32L476xx Table 72. I/O AC characteristics(1)(2) (continued) Speed Symbol Fmax Parameter Maximum frequency 10 Tr/Tf Fmax Output rise and fall time Maximum frequency 11 Tr/Tf Fm+ Fmax Tf Output rise and fall time Maximum frequency Output fall time (4) Conditions Min Max C=50 pF, 2.7 V≤VDDIOx≤3.6 V - 50 C=50 pF, 1.62 V≤VDDIOx≤2.7 V - 25 C=50 pF, 1.08 V≤VDDIOx≤1.62 V - 5 C=10 pF, 2.7 V≤VDDIOx≤3.6 V - 100(3) C=10 pF, 1.62 V≤VDDIOx≤2.7 V - 37.
PAGE 175
STM32L476xx Electrical characteristics Figure 30. I/O AC characteristics definition(1) 90% 10% 50% 50% 10% 90% t f(IO)out t r(IO)out T Maximum frequency is achieved if (t r + t f (≤ 2/3)T and if the duty cycle is (45-55%) when loaded by the specified capacitance. MS32132V2 1. Refer to Table 72: I/O AC characteristics. 6.3.15 NRST pin characteristics The NRST pin input driver uses the CMOS technology. It is connected to a permanent pullup resistor, RPU.
PAGE 176
Electrical characteristics STM32L476xx Figure 31. Recommended NRST pin protection External reset circuit(1) VDD RPU NRST(2) Internal reset Filter 0.1 μF MS19878V3 1. The reset network protects the device against parasitic resets. 2. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in Table 73: NRST pin characteristics. Otherwise the reset will not be taken into account by the device. 3.
PAGE 177
STM32L476xx 6.3.18 Electrical characteristics Analog-to-Digital converter characteristics Unless otherwise specified, the parameters given in Table 76 are preliminary values derived from tests performed under ambient temperature, fPCLK frequency and VDDA supply voltage conditions summarized in Table 23: General operating conditions. Note: It is recommended to perform a calibration after each power-up. Table 76.
PAGE 178
Electrical characteristics STM32L476xx Table 76. ADC characteristics(1) (2) (continued) Symbol Parameter Conditions Min Typ Max 2.5 3 3.5 - - 3.0 - - 3.25 - - 3.125 0.03125 - 8.00625 µs - 2.5 - 640.5 1/fADC - - - 20 µs 0.1875 - 8.
PAGE 179
STM32L476xx Electrical characteristics Table 77. Maximum ADC RAIN(1)(2) Resolution 12 bits 10 bits 8 bits 6 bits Sampling cycle @80 MHz Sampling time [ns] @80 MHz 2.5 RAIN max (Ω) Fast channels(3) Slow channels(4) 31.25 100 N/A 6.5 81.25 330 100 12.5 156.25 680 470 24.5 306.25 1500 1200 47.5 593.75 2200 1800 92.5 1156.25 4700 3900 247.5 3093.75 12000 10000 640.5 8006.75 39000 33000 2.5 31.25 120 N/A 6.5 81.25 390 180 12.5 156.25 820 560 24.5 306.
PAGE 180
Electrical characteristics STM32L476xx 2. The I/O analog switch voltage booster is enable when VDDA < 2.4 V (BOOSTEN = 1 in the SYSCFG_CFGR1 when VDDA < 2.4V). It is disable when VDDA ≥ 2.4 V. 3. Fast channels are: PC0, PC1, PC2, PC3, PA0. 4. Slow channels are: all ADC inputs except the fast channels. 180/270 Downloaded from Arrow.com.
PAGE 181
STM32L476xx Electrical characteristics Table 78. ADC accuracy - limited test conditions 1(1)(2)(3) Symbol Parameter ET Total unadjusted error EO Conditions(4) Offset error Single ended Differential Single ended Differential Single ended EG Gain error Differential ED EL Differential linearity ADC clock frequency ≤ error 80 MHz, Sampling rate ≤ 5.
PAGE 182
Electrical characteristics STM32L476xx Table 78. ADC accuracy - limited test conditions 1(1)(2)(3) (continued) Symbol THD Conditions(4) Parameter Total harmonic distortion ADC clock frequency ≤ Single 80 MHz, ended Sampling rate ≤ 5.33 Msps, VDDA = VREF+ = 3 V, Differential TA = 25 °C Min Typ Max Unit Fast channel (max speed) - -74 -73 Slow channel (max speed) - -74 -73 Fast channel (max speed) - -79 -76 Slow channel (max speed) - -79 -76 dB 1. Guaranteed by design. 2.
PAGE 183
STM32L476xx Electrical characteristics Table 79. ADC accuracy - limited test conditions 2(1)(2)(3) Symbol Parameter ET Total unadjusted error EO Conditions(4) Offset error Single ended Differential Single ended Differential Single ended EG Gain error Differential ED EL Differential linearity error ADC clock frequency ≤ 80 MHz, Sampling rate ≤ 5.
PAGE 184
Electrical characteristics STM32L476xx Table 79. ADC accuracy - limited test conditions 2(1)(2)(3) (continued) Symbol THD Conditions(4) Parameter Total harmonic distortion Fast channel (max speed) Single ADC clock frequency ≤ ended Slow channel (max speed) 80 MHz, Sampling rate ≤ 5.33 Msps, Fast channel (max speed) Differential 2 V ≤ VDDA Slow channel (max speed) Min Typ Max Unit - -74 -65 - -74 -67 - -79 -70 - -79 -71 dB 1. Guaranteed by design. 2.
PAGE 185
STM32L476xx Electrical characteristics Table 80. ADC accuracy - limited test conditions 3(1)(2)(3) Symbol Parameter ET Total unadjusted error EO Conditions(4) Offset error Single ended Differential Single ended Differential Single ended EG Gain error Differential ED EL Differential linearity ADC clock frequency ≤ error 80 MHz, Sampling rate ≤ 5.33 Msps, 1.65 V ≤ VDDA = VREF+ ≤ 3.
PAGE 186
Electrical characteristics STM32L476xx Table 80. ADC accuracy - limited test conditions 3(1)(2)(3) (continued) Symbol THD Conditions(4) Parameter Total harmonic distortion ADC clock frequency ≤ Single 80 MHz, ended Sampling rate ≤ 5.33 Msps, 1.65 V ≤ VDDA = VREF+ ≤ Differential 3.6 V, Voltage scaling Range 1 Min Typ Max Unit Fast channel (max speed) - -69 -67 Slow channel (max speed) - -71 -67 Fast channel (max speed) - -72 -71 Slow channel (max speed) - -72 -71 dB 1.
PAGE 187
STM32L476xx Electrical characteristics Table 81. ADC accuracy - limited test conditions 4(1)(2)(3) Symbol Parameter ET Total unadjusted error EO Offset error Conditions(4) Single ended Differential Single ended Differential Single ended EG Gain error Differential ED EL Differential linearity ADC clock frequency ≤ error 26 MHz, 1.65 V ≤ VDDA = VREF+ ≤ 3.
PAGE 188
Electrical characteristics STM32L476xx Table 81. ADC accuracy - limited test conditions 4(1)(2)(3) (continued) Symbol THD Conditions(4) Parameter Total harmonic distortion ADC clock frequency ≤ 26 MHz, 1.65 V ≤ VDDA = VREF+ ≤ 3.6 V, Voltage scaling Range 2 Single ended Differential Min Typ Max Unit Fast channel (max speed) - -71 -69 Slow channel (max speed) - -71 -69 Fast channel (max speed) - -73 -72 Slow channel (max speed) - -73 -72 dB 1. Guaranteed by design. 2.
PAGE 189
STM32L476xx Electrical characteristics Figure 32. ADC accuracy characteristics VSSA EG (1) Example of an actual transfer curve (2) The ideal transfer curve (3) End point correlation line 4095 4094 4093 (2) ET (3) 7 (1) 6 5 EO EL 4 3 ED 2 1 LSB IDEAL 1 0 1 2 3 4 5 6 7 ET = total unajusted error: maximum deviation between the actual and ideal transfer curves. EO = offset error: maximum deviation between the first actual transition and the first ideal one.
PAGE 190
Electrical characteristics 6.3.19 STM32L476xx Digital-to-Analog converter characteristics Table 82. DAC characteristics(1) Symbol VDDA VREF+ VREF- Parameter Analog supply voltage for DAC ON Positive reference voltage Conditions Min Typ DAC output buffer OFF (no resistive load on DAC1_OUTx pin or internal connection) 1.71 - Other modes 1.80 - DAC output buffer OFF (no resistive load on DAC1_OUTx pin or internal connection) 1.71 - Other modes 1.
PAGE 191
STM32L476xx Electrical characteristics Table 82.
PAGE 192
Electrical characteristics STM32L476xx Table 82.
PAGE 193
STM32L476xx Electrical characteristics Table 83. DAC accuracy(1) .
PAGE 194
Electrical characteristics STM32L476xx Table 83. DAC accuracy(1) (continued) Symbol Parameter SINAD Signal-to-noise and distortion ratio ENOB Effective number of bits Conditions Min Typ Max DAC output buffer ON CL ≤ 50 pF, RL ≥ 5 kΩ, 1 kHz - 70.4 - DAC output buffer OFF CL ≤ 50 pF, no RL, 1 kHz - 71 - DAC output buffer ON CL ≤ 50 pF, RL ≥ 5 kΩ, 1 kHz - 11.4 - DAC output buffer OFF CL ≤ 50 pF, no RL, 1 kHz - Unit dB bits 11.5 - 1. Guaranteed by design. 2.
PAGE 195
STM32L476xx 6.3.20 Electrical characteristics Voltage reference buffer characteristics Table 84. VREFBUF characteristics(1) Symbol Parameter Conditions Normal mode VDDA VREFBUF_ OUT Analog supply voltage Voltage reference output Degraded mode(2) Normal mode Degraded mode(2) Min Typ Max VRS = 0 2.4 - 3.6 VRS = 1 2.8 - 3.6 VRS = 0 1.65 - 2.4 VRS = 1 1.65 - 2.8 2.048 2.049(3) (3) VRS = 0 2.046 VRS = 1 2.498(3) 2.5 2.
PAGE 196
Electrical characteristics STM32L476xx Table 84. VREFBUF characteristics(1) (continued) Symbol Parameter VREFBUF IDDA(VREF consumption BUF) from VDDA Conditions Min Typ Max Iload = 0 µA - 16 25 Iload = 500 µA - 18 30 Iload = 4 mA - 35 50 Unit µA 1. Guaranteed by design, unless otherwise specified. 2. In degraded mode, the voltage reference buffer can not maintain accurately the output voltage which will follow (VDDA drop voltage). 3. Guaranteed by test in production. 4.
PAGE 197
STM32L476xx 6.3.21 Electrical characteristics Comparator characteristics Table 85. COMP characteristics(1) Symbol Conditions Min Typ Max Analog supply voltage - 1.62 - 3.6 Comparator input voltage range - 0 - VDDA V VBG(2) Scaler input voltage - VSC Scaler offset voltage - VDDA VIN IDDA(SCALER) Parameter VREFINT - ±5 ±10 mV BRG_EN=0 (bridge disable) - 200 300 nA BRG_EN=1 (bridge enable) - 0.8 1 µA - 100 200 µs VDDA ≥ 2.7 V - - 5 VDDA < 2.
PAGE 198
Electrical characteristics STM32L476xx Table 85.
PAGE 199
STM32L476xx Electrical characteristics Table 86.
PAGE 200
Electrical characteristics STM32L476xx Table 86.
PAGE 201
STM32L476xx Electrical characteristics Table 86.
PAGE 202
Electrical characteristics 6.3.23 STM32L476xx Temperature sensor characteristics Table 87. TS characteristics Symbol Parameter TL(1) Min Typ Max Unit - ±1 ±2 °C 2.3 2.5 2.7 mV/°C 0.742 0.76 0.
PAGE 203
STM32L476xx 6.3.25 Electrical characteristics LCD controller characteristics The devices embed a built-in step-up converter to provide a constant LCD reference voltage independently from the VDD voltage. An external capacitor Cext must be connected to the VLCD pin to decouple this converter. Table 90. LCD controller characteristics(1) Symbol Parameter Conditions Min Typ Max VLCD LCD external voltage - - 3.6 VLCD0 LCD internal reference voltage 0 - 2.
PAGE 204
Electrical characteristics STM32L476xx 1. Guaranteed by design. 2. LCD enabled with 3 V internal step-up active, 1/8 duty, 1/4 bias, division ratio= 64, all pixels active, no LCD connected. 204/270 Downloaded from Arrow.com.
PAGE 205
STM32L476xx 6.3.26 Electrical characteristics DFSDM characteristics Unless otherwise specified, the parameters given in Table 91 for DFSDM are derived from tests performed under the ambient temperature, fAPB2 frequency and VDD supply voltage conditions summarized in Table 23: General operating conditions. • Output speed is set to OSPEEDRy[1:0] = 10 • Capacitive load C = 30 pF • Measurement points are done at CMOS levels: 0.5 ₓ VDD Refer to Section 6.3.
PAGE 206
Electrical characteristics STM32L476xx ')6'0B &.,1,1\ ')6'0B'$7$,1\ 63, WLPLQJ 63,&.6(/ Figure 16: DFSDM timing diagram WZO WZK WU WI 63,&.6(/ WVX WK 6,73 WVX WK 6,73 ')6'0B&.287 63,&.6(/ WZO WU WZK WI 63,&.6(/ ')6'0B'$7$,1\ WVX ')6'0B'$7$,1\ 0DQFKHVWHU WLPLQJ 63, WLPLQJ 63,&.6(/ 63,&.6(/ WK 6,73 WVX WK 6,73 6,73 6,73 5HFRYHUHG FORFN 5HFRYHUHG GDWD 06Y 9 6.3.
PAGE 207
STM32L476xx Electrical characteristics Table 92. TIMx(1) characteristics Symbol tres(TIM) Parameter Timer resolution time Conditions Min Max Unit - 1 - tTIMxCLK fTIMxCLK = 80 MHz 12.5 - ns 0 fTIMxCLK/2 MHz 0 40 MHz TIMx (except TIM2 and TIM5) - 16 TIM2 and TIM5 - 32 - 1 65536 tTIMxCLK fTIMxCLK = 80 MHz 0.0125 819.2 µs - - 65536 × 65536 tTIMxCLK fTIMxCLK = 80 MHz - 53.
PAGE 208
Electrical characteristics 6.3.28 STM32L476xx Communication interfaces characteristics I2C interface characteristics The I2C interface meets the timings requirements of the I2C-bus specification and user manual rev. 03 for: • Standard-mode (Sm): with a bit rate up to 100 kbit/s • Fast-mode (Fm): with a bit rate up to 400 kbit/s • Fast-mode Plus (Fm+): with a bit rate up to 1 Mbit/s.
PAGE 209
STM32L476xx Electrical characteristics SPI characteristics Unless otherwise specified, the parameters given in Table 96 for SPI are derived from tests performed under the ambient temperature, fPCLKx frequency and supply voltage conditions summarized in Table 23: General operating conditions. • Output speed is set to OSPEEDRy[1:0] = 11 • Capacitive load C = 30 pF • Measurement points are done at CMOS levels: 0.5 ₓ VDD Refer to Section 6.3.
PAGE 210
Electrical characteristics STM32L476xx Table 96. SPI characteristics(1) (continued) Symbol Parameter Min Typ Max Slave mode 2.7 < VDD < 3.6 V Voltage Range 1 - 12.5 19 Slave mode 1.71 < VDD < 3.6 V Voltage Range 1 - 12.5 30 Slave mode 1.71 < VDD < 3.6 V Voltage Range 2 - 12.5 33 Slave mode 1.08 < VDDIO2 < 1.32 V(3) - 25 62.5 tv(MO) Master mode - 2.5 12.
PAGE 211
STM32L476xx Electrical characteristics Figure 36. SPI timing diagram - slave mode and CPHA = 1 NSS input SCK input tc(SCK) tsu(NSS) tw(SCKH) ta(SO) tw(SCKL) tf(SCK) th(NSS) CPHA=1 CPOL=0 CPHA=1 CPOL=1 tv(SO) th(SO) First bit OUT MISO output tsu(SI) MOSI input Next bits OUT tr(SCK) tdis(SO) Last bit OUT th(SI) First bit IN Next bits IN Last bit IN MSv41659V1 1. Measurement points are done at CMOS levels: 0.3 VDD and 0.7 VDD. Figure 37.
PAGE 212
Electrical characteristics STM32L476xx Quad SPI characteristics Unless otherwise specified, the parameters given in Table 97 and Table 98 for Quad SPI are derived from tests performed under the ambient temperature, fAHB frequency and VDD supply voltage conditions summarized in Table 23: General operating conditions, with the following configuration: • Output speed is set to OSPEEDRy[1:0] = 11 • Capacitive load C = 15 or 20 pF • Measurement points are done at CMOS levels: 0.5 ₓ VDD Refer to Section 6.3.
PAGE 213
STM32L476xx Electrical characteristics Table 98. QUADSPI characteristics in DDR mode(1) Symbol Parameter FCK 1/t(CK) Quad SPI clock frequency tw(CKH) Quad SPI clock high and low time tw(CKL) tsf(IN);tsr(IN) Data input setup time thf(IN); thr(IN) Data input hold time tvf(OUT);tvr(OUT) Data output valid time thf(OUT); thr(OUT) Data output hold time Conditions Min Typ Max Unit 1.71 < VDD < 3.6 V, CLOAD = 20 pF Voltage Range 1 - - 40 2 < VDD < 3.
PAGE 214
Electrical characteristics STM32L476xx SAI characteristics Unless otherwise specified, the parameters given in Table 99 for SAI are derived from tests performed under the ambient temperature, fPCLKx frequency and VDD supply voltage conditions summarized inTable 23: General operating conditions, with the following configuration: • Output speed is set to OSPEEDRy[1:0] = 10 • Capacitive load C = 30 pF • Measurement points are done at CMOS levels: 0.5 ₓ VDD Refer to Section 6.3.
PAGE 215
STM32L476xx Electrical characteristics Table 99. SAI characteristics(1) (continued) Symbol tv(SD_B_ST) th(SD_B_ST) tv(SD_A_MT) th(SD_A_MT) Parameter Conditions Data output valid time Data output hold time Data output valid time Data output hold time Min Max Slave transmitter (after enable edge) 2.7 ≤ VDD ≤ 3.6 - 22 Slave transmitter (after enable edge) 1.71 ≤ VDD ≤ 3.6 - 34 Slave transmitter (after enable edge) 10 - Master transmitter (after enable edge) 2.7 ≤ VDD ≤ 3.
PAGE 216
Electrical characteristics STM32L476xx Figure 41.
PAGE 217
STM32L476xx Electrical characteristics Table 100. SD / MMC dynamic characteristics, VDD=2.7 V to 3.6 V(1) (continued) Symbol Parameter Conditions Min Typ Max Unit CMD, D outputs (referenced to CK) in SD default mode tOVD Output valid default time SD fPP = 50 MHz - 4.5 5 ns tOHD Output hold default time SD fPP = 50 MHz 0 - - ns 1. Guaranteed by characterization results. Table 101. eMMC dynamic characteristics, VDD = 1.71 V to 1.
PAGE 218
Electrical characteristics STM32L476xx Figure 43. SD default mode CK tOVD tOHD D, CMD (output) ai14888 USB OTG full speed (FS) characteristics The STM32L476xx USB interface is fully compliant with the USB specification version 2.0 and is USB-IF certified (for Full-speed device operation). Table 102. USB OTG DC electrical characteristics Symbol Parameter Conditions Min(1) Typ Max(1) Unit VDDUSB USB OTG full speed transceiver operating voltage - 3.0(2) - 3.
PAGE 219
STM32L476xx Electrical characteristics Figure 44. USB OTG timings – definition of data signal rise and fall time Cross over points Differential data lines VCRS VSS tf tr ai14137b Table 103.
PAGE 220
Electrical characteristics STM32L476xx Table 104. USB BCD DC electrical characteristics(1) (continued) Symbol Parameter Conditions Min. Typ. Max. Unit VDAT_REF Data detect voltage - 0.25 - 0.4 V VDP_SRC D+ source voltage - 0.5 - 0.7 V VDM_SRC D- source voltage - 0.5 - 0.7 V IDP_SINK D+ sink current - 25 - 175 μA IDM_SINK D- sink current - 25 - 175 μA 1. Guaranteed by design. CAN (controller area network) interface Refer to Section 6.3.
PAGE 221
STM32L476xx 6.3.29 Electrical characteristics FSMC characteristics Unless otherwise specified, the parameters given in Table 105 to Table 118 for the FMC interface are derived from tests performed under the ambient temperature, fHCLK frequency and VDD supply voltage conditions summarized in Table 23, with the following configuration: • Output speed is set to OSPEEDRy[1:0] = 11 • Capacitive load C = 30 pF • Measurement points are done at CMOS levels: 0.5VDD Refer to Section 6.3.
PAGE 222
Electrical characteristics STM32L476xx Figure 45. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms tw(NE) FMC_NE tv(NOE_NE) t w(NOE) t h(NE_NOE) FMC_NOE FMC_NWE tv(A_NE) FMC_A[25:0] t h(A_NOE) Address tv(BL_NE) t h(BL_NOE) FMC_NBL[1:0] t h(Data_NE) t su(Data_NOE) th(Data_NOE) t su(Data_NE) Data FMC_D[15:0] t v(NADV_NE) tw(NADV) FMC_NADV (1) FMC_NWAIT th(NE_NWAIT) tsu(NWAIT_NE) MS32753V1 222/270 Downloaded from Arrow.com.
PAGE 223
STM32L476xx Electrical characteristics Table 105. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings(1)(2) Symbol Min Max 2THCLK-0.5 2THCLK+0.5 0 1 2THCLK-0.5 2THCLK+1 FMC_NOE high to FMC_NE high hold time 0 - FMC_NEx low to FMC_A valid - 3.
PAGE 224
Electrical characteristics STM32L476xx Figure 46. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms tw(NE) FMC_NEx FMC_NOE tv(NWE_NE) tw(NWE) t h(NE_NWE) FMC_NWE tv(A_NE) FMC_A[25:0] th(A_NWE) Address tv(BL_NE) FMC_NBL[1:0] th(BL_NWE) NBL tv(Data_NE) th(Data_NWE) Data FMC_D[15:0] t v(NADV_NE) FMC_NADV (1) tw(NADV) FMC_NWAIT th(NE_NWAIT) tsu(NWAIT_NE) MS32754V1 Table 107.
PAGE 225
STM32L476xx Electrical characteristics Table 108. Asynchronous non-multiplexed SRAM/PSRAM/NOR write-NWAIT timings(1)(2) Symbol Parameter Min Max FMC_NE low time 8THCLK+0.5 8THCLK+0.5 FMC_NWE low time 6THCLK-0.5 6THCLK+0.5 tsu(NWAIT_NE) FMC_NWAIT valid before FMC_NEx high 6THCLK+2 - th(NE_NWAIT) FMC_NEx hold time after FMC_NWAIT invalid 4THCLK+2 - tw(NE) tw(NWE) Unit ns 1. CL = 30 pF. 2. Guaranteed by characterization results. Figure 47.
PAGE 226
Electrical characteristics STM32L476xx Table 109. Asynchronous multiplexed PSRAM/NOR read timings(1)(2) Symbol tw(NE) tv(NOE_NE) tw(NOE) th(NE_NOE) tv(A_NE) Parameter Min Max FMC_NE low time 3THCLK-0.5 3THCLK+2 FMC_NEx low to FMC_NOE low 2THCLK-0.5 2THCLK+0.5 FMC_NOE low time THCLK+0.5 THCLK+1 FMC_NOE high to FMC_NE high hold time 0 - FMC_NEx low to FMC_A valid - 3 0 1 THCLK-0.
PAGE 227
STM32L476xx Electrical characteristics Figure 48. Asynchronous multiplexed PSRAM/NOR write waveforms tw(NE) FMC_ NEx FMC_NOE tv(NWE_NE) tw(NWE) t h(NE_NWE) FMC_NWE th(A_NWE) tv(A_NE) FMC_ A[25:16] Address tv(BL_NE) th(BL_NWE) FMC_ NBL[1:0] NBL t v(A_NE) FMC_ AD[15:0] t v(Data_NADV) Address th(Data_NWE) Data th(AD_NADV) t v(NADV_NE) tw(NADV) FMC_NADV FMC_NWAIT th(NE_NWAIT) tsu(NWAIT_NE) MS32756V1 DS10198 Rev 8 227/270 238 Downloaded from Arrow.com.
PAGE 228
Electrical characteristics STM32L476xx Table 111. Asynchronous multiplexed PSRAM/NOR write timings(1)(2) Symbol Min Max FMC_NE low time 4THCLK-0.5 4THCLK+2 FMC_NEx low to FMC_NWE low THCLK-0.5 THCLK+1 2xTHCLK-1.5 2xTHCLK+1. 5 THCLK-0.5 - FMC_NEx low to FMC_A valid - 3 FMC_NEx low to FMC_NADV low 0 1 THCLK-0.
PAGE 229
STM32L476xx Electrical characteristics In all timing tables, the THCLK is the HCLK clock period. Figure 49.
PAGE 230
Electrical characteristics STM32L476xx Table 113. Synchronous multiplexed NOR/PSRAM read timings(1)(2) Symbol Min Max 2THCLK-1 - - 2 THCLK+0.5 - td(CLKL-NADVL) FMC_CLK low to FMC_NADV low - 2.5 td(CLKL-NADVH) FMC_CLK low to FMC_NADV high 1 - - 3.5 THCLK - - 1.5 THCLK+1 - tw(CLK) Parameter FMC_CLK period td(CLKL-NExL) FMC_CLK low to FMC_NEx low (x=0..
PAGE 231
STM32L476xx Electrical characteristics Figure 50.
PAGE 232
Electrical characteristics STM32L476xx Table 114. Synchronous multiplexed PSRAM write timings(1)(2) Symbol tw(CLK) Parameter FMC_CLK period 2THCLK-1 - - 2 THCLK+0.5 - FMC_CLK low to FMC_NEx low (x=0..2) td(CLKH-NExH) FMC_CLK high to FMC_NEx high (x= 0…2) td(CLKL-NADVL) FMC_CLK low to FMC_NADV low - 2.5 td(CLKL-NADVH) FMC_CLK low to FMC_NADV high 1 - td(CLKL-AV) FMC_CLK low to FMC_Ax valid (x=16…25) - 3.
PAGE 233
STM32L476xx Electrical characteristics Figure 51.
PAGE 234
Electrical characteristics STM32L476xx 1. CL = 30 pF. 2. Guaranteed by characterization results. Figure 52.
PAGE 235
STM32L476xx Electrical characteristics Table 116. Synchronous non-multiplexed PSRAM write timings(1)(2) Symbol tw(CLK) Parameter FMC_CLK period Min Max 2THCLK-0.5 - - 2 THCLK+0.5 - td(CLKL-NExL) FMC_CLK low to FMC_NEx low (x=0..2) td(CLKH-NExH) FMC_CLK high to FMC_NEx high (x= 0…2) td(CLKL-NADVL) FMC_CLK low to FMC_NADV low - 2 td(CLKL-NADVH) FMC_CLK low to FMC_NADV high 2.5 - - 5 THCLK-1 - - 2 THCLK-1 - - 4.5 1.
PAGE 236
Electrical characteristics STM32L476xx Figure 53. NAND controller waveforms for read access FMC_NCEx ALE (FMC_A17) CLE (FMC_A16) FMC_NWE th(NOE-ALE) td(NCE-NOE) FMC_NOE (NRE) tsu(D-NOE) th(NOE-D) FMC_D[15:0] MSv38003V1 Figure 54. NAND controller waveforms for write access FMC_NCEx ALE (FMC_A17) CLE (FMC_A16) th(NWE-ALE) td(NCE-NWE) FMC_NWE FMC_NOE (NRE) th(NWE-D) tv(NWE-D) FMC_D[15:0] MSv38004V1 Figure 55.
PAGE 237
STM32L476xx Electrical characteristics Figure 56. NAND controller waveforms for common memory write access FMC_NCEx ALE (FMC_A17) CLE (FMC_A16) td(NCE-NWE) tw(NWE) th(NOE-ALE) FMC_NWE FMC_NOE td(D-NWE) tv(NWE-D) th(NWE-D) FMC_D[15:0] MSv38006V1 Table 117.
PAGE 238
Electrical characteristics 6.3.30 STM32L476xx SWPMI characteristics The Single Wire Protocol Master Interface (SWPMI) and the associated SWPMI_IO transceiver are compliant with the ETSI TS 102 613 technical specification. Table 119. SWPMI electrical characteristics(1) Symbol Parameter Conditions tSWPSTART SWPMI regulator startup time tSWPBIT SWP bit duration Min Typ - - 300 VCORE voltage range 1 500 - - VCORE voltage range 2 620 - - SWP Class B 2.7 V ≤ VDD ≤ 3,3V 1.
PAGE 239
STM32L476xx 7 Package information Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. 7.1 LQFP144 package information Figure 57. LQFP - 144-pin, 20 x 20 mm low-profile quad flat package outline SEATING PLANE c A1 A2 A C 0.
PAGE 240
Package information STM32L476xx Table 120. LQFP - 144-pin, 20 x 20 mm low-profile quad flat package mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A - - 1.600 - - 0.0630 A1 0.050 - 0.150 0.0020 - 0.0059 A2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 - 0.200 0.0035 - 0.0079 D 21.800 22.000 22.200 0.8583 0.8661 0.8740 D1 19.800 20.000 20.200 0.7795 0.7874 0.7953 D3 - 17.500 - - 0.
PAGE 241
STM32L476xx Package information Figure 58. LQFP - 144-pin,20 x 20 mm low-profile quad flat package recommended footprint 108 109 73 1.35 72 0.35 0.5 19.9 17.85 22.6 144 37 1 36 19.9 22.6 ai14905e 1. Dimensions are expressed in millimeters. DS10198 Rev 8 241/270 263 Downloaded from Arrow.com.
PAGE 242
Package information STM32L476xx Device marking The following figure gives an example of topside marking orientation versus pin 1 identifier location. The printed markings may differ depending on the supply chain. Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below. Figure 59.
PAGE 243
STM32L476xx 7.2 Package information UFBGA144 package information Figure 60. UFBGA - 144-pin, 10 x 10 mm, 0.80 mm pitch, ultra fine pitch ball grid array package outline C Seating plane ddd Z A4 A3 A2 A1 A E1 e A1 ball A1 ball identifier index area F A E A F D1 D e B M 12 1 BOTTOM VIEW Øb (144 balls) Ø eee M C A B Ø fff M C TOP VIEW A02Y_ME_V2 1. Drawing is not to scale. Table 121. UFBGA - 144-pin, 10 x 10 mm, 0.
PAGE 244
Package information STM32L476xx Table 121. UFBGA - 144-pin, 10 x 10 mm, 0.80 mm pitch, ultra fine pitch ball grid array package mechanical data (continued) inches(1) millimeters Symbol Min. Typ. Max. Min. Typ. Max. ddd - - 0.080 - - 0.0039 eee - - 0.150 - - 0.0059 fff - - 0.080 - - 0.0020 1. Values in inches are converted from mm and rounded to 4 decimal digits. Figure 61. UFBGA - 144-pin, 10 x 10 mm, 0.
PAGE 245
STM32L476xx Package information Figure 62. UFBGA144 marking (package top view) Product identification(1) STM32L476 ZGJ6 Y Additional information Date code Y WW Ball A1 indentifier MSv50913V1 1. Parts marked as ES or E or accompanied by an Engineering Sample notification letter are not yet qualified and therefore not approved for use in production. ST is not responsible for any consequences resulting from such use.
PAGE 246
Package information 7.3 STM32L476xx UFBGA132 package information Figure 63. UFBGA - 132-ball, 7 x 7 mm ultra thin fine pitch ball grid array package outline A1 ball identifier A B E1 e E Z A Z D1 D e M 12 BOTTOM VIEW 1 Øb (132 balls) Øeee M C A B Ø fff M C TOP VIEW A4 ddd C A2 A3 A1 A b SEATING PLANE UFBGA132_A0G8_ME_V2 1. Drawing is not to scale. Table 123.
PAGE 247
STM32L476xx Package information Table 123. UFBGA - 132-ball, 7 x 7 mm ultra thin fine pitch ball grid array package mechanical data (continued) inches(1) millimeters Symbol Min Typ Max Min Typ Max e - 0.500 - - 0.0197 - Z - 0.750 - - 0.0295 - ddd - 0.080 - - 0.0031 - eee - 0.150 - - 0.0059 - fff - 0.050 - - 0.0020 - 1. Values in inches are converted from mm and rounded to 4 decimal digits. Figure 64.
PAGE 248
Package information STM32L476xx The printed markings may differ depending on the supply chain. Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below. Figure 65. UFBGA132 marking (package top view) Product identification(1) STM32L 476QGI6 Y WW 3 Ball A1 indentifier Date code Revision code MSv36851V3 1.
PAGE 249
STM32L476xx 7.4 Package information LQFP100 package information Figure 66. LQFP - 100 pins, 14 x 14 mm low-profile quad flat package outline 0.25 mm c A1 A A2 SEATING PLANE C GAUGE PLANE D A1 K ccc C L D1 L1 D3 51 75 50 100 26 PIN 1 1 IDENTIFICATION E E3 E1 b 76 25 e 1L_ME_V5 1. Drawing is not to scale. Table 125. LQFP - 100 pins, 14 x 14 mm low-profile quad flat package mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A - - 1.600 - - 0.
PAGE 250
Package information STM32L476xx Table 125. LQFP - 100 pins, 14 x 14 mm low-profile quad flat package mechanical data (continued) inches(1) millimeters Symbol Min Typ Max Min Typ Max D3 - 12.000 - - 0.4724 - E 15.800 16.000 16.200 0.6220 0.6299 0.6378 E1 13.800 14.000 14.200 0.5433 0.5512 0.5591 E3 - 12.000 - - 0.4724 - e - 0.500 - - 0.0197 - L 0.450 0.600 0.750 0.0177 0.0236 0.0295 L1 - 1.000 - - 0.0394 - k 0.0° 3.5° 7.0° 0.0° 3.5° 7.
PAGE 251
STM32L476xx Package information Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below. Figure 68. LQFP100 marking (package top view) Product identification(1) STM32L476 VGT6 Optional gate mark 3 Revision code Date code Y WW Pin 1 indentifier MSv36845V2 1. Parts marked as ES or E or accompanied by an Engineering Sample notification letter are not yet qualified and therefore not approved for use in production.
PAGE 252
Package information 7.5 STM32L476xx WLCSP81 package information Figure 69. WLCSP - 81-ball, 4.4084 x 3.7594 mm, 0.4 mm pitch wafer level chip scale package outline e1 bbb Z A1 ball location e A1 ball location D A e Detail A E e2 J G 1 9 Bottom view Bump side aaa A3 F Top view Wafer back side A2 A Side view Detail A rotated by 90° A1 eee Z Ø ccc Øddd b M ZXY M Z Seating plane Z A05Z_ME_V1 1. Drawing is not to scale. Table 126. WLCSP- 81-ball, 4.4084 x 3.7594 mm, 0.
PAGE 253
STM32L476xx Package information Table 126. WLCSP- 81-ball, 4.4084 x 3.7594 mm, 0.4 mm pitch wafer level chip scale package mechanical data (continued) inches(1) millimeters Symbol Min Typ Max Min Typ Max F - 0.6042 - - 0.0238 - G - 0.2797 - - 0.0110 - aaa - - 0.100 - - 0.0039 bbb - - 0.100 - - 0.0039 ccc - - 0.100 - - 0.0039 ddd - - 0.050 - - 0.0020 eee - - 0.050 - - 0.0020 1. Values in inches are converted from mm and rounded to 4 decimal digits.
PAGE 254
Package information STM32L476xx Figure 71. WLCSP81 marking (package top view) Ball A1 identifier L476MEY6 Product identification (1) Revision code Y WW 3 Date code MSv40100V1 1. Parts marked as ES or E or accompanied by an Engineering Sample notification letter are not yet qualified and therefore not approved for use in production. ST is not responsible for any consequences resulting from such use.
PAGE 255
STM32L476xx 7.6 Package information WLCSP72 package information Figure 72. WLCSP - 72-ball, 4.4084 x 3.7594 mm, 0.4 mm pitch wafer level chip scale package outline bbb Z e1 D e e Detail A X Y E e2 G aaa A3 A2 A F Bottom view Bump side A1 ball location Top view Wafer back side Side view Bump eee Z A1 Ø ccc Øddd b (72X) M Z XY M Z Z Seating plane Detail A rotated by 90° A02R_ME_V1 1. Drawing is not to scale. Table 128. WLCSP - 72-ball, 4.4084 x 3.7594 mm, 0.
PAGE 256
Package information STM32L476xx Table 128. WLCSP - 72-ball, 4.4084 x 3.7594 mm, 0.4 mm pitch wafer level chip scale package mechanical data (continued) inches(1) millimeters Symbol Min Typ Max Min Typ Max aaa - 0.100 - - 0.0039 - bbb - 0.100 - - 0.0039 - ccc - 0.100 - - 0.0039 - ddd - 0.050 - - 0.0020 - eee - 0.050 - - 0.0020 - 1. Values in inches are converted from mm and rounded to 4 decimal digits. 2. Back side coating 3.
PAGE 257
STM32L476xx Package information The printed markings may differ depending on the supply chain. Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below. Figure 74. WLCSP72 marking (package top view) Ball A1 identifier L476JGY6 Product identification (1) Revision code Date code Y WW 3 MSv36870V3 1.
PAGE 258
Package information 7.7 STM32L476xx LQFP64 package information Figure 75. LQFP - 64 pins, 10 x 10 mm low-profile quad flat package outline 0.25 mm GAUGE PLANE c A1 A A2 SEATING PLANE C A1 ccc C D D1 D3 K L L1 33 48 32 49 64 PIN 1 IDENTIFICATION E E1 E3 b 17 16 1 e 5W_ME_V3 1. Drawing is not to scale. Table 130. LQFP - 64 pins, 10 x 10 mm low-profile quad flat package mechanical data inches(1) millimeters Symbol 258/270 Downloaded from Arrow.com.
PAGE 259
STM32L476xx Package information Table 130. LQFP - 64 pins, 10 x 10 mm low-profile quad flat package mechanical data (continued) inches(1) millimeters Symbol Min Typ Max Min Typ Max E3 - 7.500 - - 0.2953 - e - 0.500 - - 0.0197 - K 0° 3.5° 7° 0° 3.5° 7° L 0.450 0.600 0.750 0.0177 0.0236 0.0295 L1 - 1.000 - - 0.0394 - ccc - - 0.080 - - 0.0031 1. Values in inches are converted from mm and rounded to 4 decimal digits. Figure 76.
PAGE 260
Package information STM32L476xx Figure 77. LQFP64 marking (package top view) Revision code 3 Product identification(1) STM32L476 RGT6 Y WW Date code Pin 1 identifier MSv36854V3 1. Parts marked as ES or E or accompanied by an Engineering Sample notification letter are not yet qualified and therefore not approved for use in production. ST is not responsible for any consequences resulting from such use.
PAGE 261
STM32L476xx 7.8 Package information Thermal characteristics The maximum chip junction temperature (TJmax) must never exceed the values given in Table 22: General operating conditions.
PAGE 262
Package information STM32L476xx Each temperature range suffix corresponds to a specific guaranteed ambient temperature at maximum dissipation and, to a specific maximum junction temperature. As applications do not commonly use the STM32L476xx at maximum dissipation, it is useful to calculate the exact power consumption and junction temperature to determine which temperature range will be best suited to the application.
PAGE 263
STM32L476xx Package information Using the values obtained in Table 131 TJmax is calculated as follows: – For LQFP64, 45 °C/W TJmax = 100 °C + (45 °C/W × 134 mW) = 100 °C + 6.03 °C = 106.03 °C This is above the range of the suffix 6 version parts (–40 < TJ < 105 °C). In this case, parts must be ordered at least with the temperature range suffix 7 (see Section 8: Ordering information) unless we reduce the power dissipation in order to be able to use suffix 6 parts.
PAGE 264
Ordering information 8 STM32L476xx Ordering information Table 132.
PAGE 265
STM32L476xx 9 Revision history Revision history Table 133. Document revision history Date Revision 29-May-2015 1 Initial release. 15-Jun-2015 2 Updated Table 1: Device summary and Table 85: COMP characteristics. 3 Changed alternate function pin name “SWDAT” into “SWDIO” in all the document. Updated Section 3.9.1: Power supply schemes. Updated Section 3.15.1: Temperature sensor. In all Section 6: Electrical characteristics, renamed table footnotes related to test and characterization.
PAGE 266
Revision history STM32L476xx Table 133. Document revision history (continued) Date 03-Dec-2015 06-Jul-2017 266/270 Downloaded from Arrow.com. Revision Changes 4 In all the document: – Stop 1 with main regulator becomes Stop 0 – Stop 1 with low-power regulator remains as Stop 1.
PAGE 267
STM32L476xx Revision history Table 133. Document revision history (continued) Date 06-Jul-2017 Revision Changes 5 (continued) – Figure 7: STM32L476Zx, external SMPS device, LQFP144 pinout(1) – Figure 12: STM32L476Mx WLCSP81 ballout(1) – Section 6.3.16: Extended interrupt and event controller input (EXTI) characteristics – Section 6.3.
PAGE 268
Revision history STM32L476xx Table 133. Document revision history (continued) Date 06-Jul-2017 268/270 Downloaded from Arrow.com. Revision Changes 5 (continued) – Section 3.14.2: Extended interrupt/event controller (EXTI) – Section 3.24.6: Independent watchdog (IWDG) – Section 3.27: Universal synchronous/asynchronous receiver transmitter (USART) – Section 3.28: Low-power universal asynchronous receiver transmitter (LPUART) – Section 3.
PAGE 269
STM32L476xx Revision history Table 133.
PAGE 270
STM32L476xx IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement.