Datasheet

DS10198 Rev 8 113/270
STM32L476xx Electrical characteristics
238
6.1.6 Power supply scheme
Figure 20. Power supply scheme
Caution: Each power supply pair (V
DD
/V
SS
, V
DDA
/V
SSA
etc.) must be decoupled with filtering ceramic
capacitors as shown above. These capacitors must be placed as close as possible to, or
V
DDIO2
V
DD
MS35001V1
Level shifter
IO
logic
Kernel logic
(CPU, Digital
& Memories)
Backup circuitry
(LSE, RTC,
Backup registers)
IN
OUT
Regulator
GPIOs
1.55 – 3.6 V
IN
OUT
GPIOs
n x 100 nF
+1 x 4.7 μF
m x100 nF
Level shifter
IO
logic
+4.7 μF
m x V
DDIO2
m x V
SS
n x V
SS
n x V
DD
V
BAT
V
CORE
Power switch
V
DDIO2
V
DDIO1
ADCs/
DACs/
OPAMPs/
COMPs/
VREF
V
REF+
V
REF-
V
DDA
10 nF
+1 μF
V
DDA
V
SSA
MS35001V2
V
DDIO2
V
DD
Level shifter
IO
logic
Kernel logic
(CPU, Digital
& Memories)
Backup circuitry
(LSE, RTC,
Backup registers)
IN
OUT
Regulator
GPIOs
1.55 – 3.6 V
IN
OUT
GPIOs
n x 100 nF
+1 x 4.7 μF
m x100 nF
Level shifter
IO
logic
+4.7 μF
m x VDDIO2
m x VSS
n x VSS
n x VDD
VBAT
V
CORE
Power switch
V
DDIO2
V
DDIO1
ADCs/
DACs/
OPAMPs/
COMPs/
VREF
V REF+
V REF-
V
DDA
10 nF
+1 μF
VDDA
VSSA
V
REF
100 nF
+1 μF
MSv45701V1
V
DDIO2
V
DD
Level shifter
IO
logic
Kernel logic
(CPU, Digital
& Memories)
Backup circuitry
(LSE, RTC,
Backup registers)
IN
OUT
Regulator
GPIOs
1.55 – 3.6 V
IN
OUT
GPIOs
n x 100 nF
+1 x 4.7 μF
m x100 nF
Level shifter
IO
logic
+4.7 μF
m x VDDIO2
m x VSS
n x VSS
n x VDD
VBAT
V
CORE
Power switch
V
DDIO2
V
DDIO1
ADCs/
DACs/
OPAMPs/
COMPs/
VREFBUF
VREF+
VREF-
V
DDA
10 nF
+1 μF
VDDA
VSSA
V
REF
100 nF
+1 μF
1.05 – 1.32 V
2 x VDD12
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