Datasheet

DS10198 Rev 8 17/270
STM32L476xx Description
60
Figure 1. STM32L476xx block diagram
Note: AF: alternate function on I/O pins.
MS31263V8
USB
OTG
Flash
up to
1 MB
Flexible static memory controller (FSMC):
SRAM, PSRAM, NOR Flash,
NAND Flash
GPIO PORT A
AHB/APB2
EXT IT. WKUP
114 AF
PA[15:0]
TIM1 / PWM
3 compl. channels (TIM1_CH[1:3]N),
4 channels (TIM1_CH[1:4]),
ETR, BKIN, BKIN2 as AF
USART1
RX, TX, CK,CTS,
RTS as AF
SPI1
MOSI, MISO,
SCK, NSS as AF
APB260 M Hz
APB1 30MHz
MOSI, MISO, SCK, NSS as AF
DAC1_OUT1
ITF
WWDG
RTC_TS
OSC32_IN
OSC32_OUT
smcard
IrDA
16b
SDIO / MMC
D[7:0]
CMD, CK as AF
VBAT = 1.55 to 3.6 V
SCL, SDA, SMBA as AF
JTAG & SW
ARM Cortex-M4
80 MHz
FPU
NVIC
ETM
MPU
DMA2
ART
ACCEL/
CACHE
CLK, NE[4:1], NL, NBL[1:0],
A[25:0], D[15:0], NOE, NWE,
NWAIT, NCE3, INT3 as AF
RNG
FIFO
@ VDDA
BOR
Supply
supervision
PVD, PVM
Int
reset
XTAL 32 kHz
MAN AGT
RTC
FCLK
Standby
interface
IWDG
@VBAT
@ VDD
@VDD
AWU
Reset & clock
control
PCLKx
Voltage
regulator
3.3 to 1.2 V
VDD
Power management
@ VDD
RTC_TAMPx
Backup register
AHB bus-matrix
TIM15
2 channels,
1 compl. channel, BKIN as AF
TIM6
TIM7
TIM2
TIM3
TIM4
TIM5
USART2
USART3
I2C1/SMBUS
D-BUS
FIFO
APB1 80 MHz (max)
SRAM 96 KB
SRAM 32 KB
I-BUS
S-BUS
DMA1
PB[15:0]
PC[15:0]
PD[15:0]
PE[15:0]
PF[15:0]
PG[15:0]
PH[1:0]
GPIO PORT B
GPIO PORT C
GPIO PORT D
GPIO PORT E
GPIO PORT F
GPIO PORT G
GPIO PORT H
TIM8 / PWM
16b
16b
TIM16
16b
TIM17
16b
3 compl. channels (TIM1_CH[1:3]N),
4 channels (TIM1_CH[1:4]),
ETR, BKIN, BKIN2 as AF
1 channel,
1 compl. channel, BKIN as AF
1 channel,
1 compl. channel, BKIN as AF
DAC1_OUT2
16b
16b
SCL, SDA, SMBA as AF
SCL, SDA, SMBA as AF
MOSI, MISO, SCK, NSS as AF
TX, RX as AF
RX, TX, CTS, RTS as AF
RX, TX, CTS, RTS as AF
RX, TX, CK, CTS, RTS as AF
RX, TX, CK, CTS, RTS as AF
smcard
IrDA
smcard
IrDA
32b
16b
16b
32b
4 channels, ETR as AF
4 channels, ETR as AF
4 channels, ETR as AF
4 channels, ETR as AF
AHB/APB1
OSC_IN
OSC_OUT
HCLKx
XTAL OSC
4- 16MHz
8 analog inputs common
to the 3 ADCs
VREF+
USAR T 2MBps
Temperature sensor
ADC1
ADC2
ADC3
IF
ITF
@ VDDA
8 analog inputs common
to the ADC1 & 2
8 analog inputs for ADC3
SAI1
MCLK_A, SD_A, FS_A, SCK_A, EXTCLK
MCLK_B, SD_B, FS_B, SCK_B as AF
SAI2
MCLK_A, SD_A, FS_A, SCK_A, EXTCLK
MCLK_B, SD_B, FS_B, SCK_B as AF
DFSDM
SDCKIN[7:0], SDDATIN[7:0],
SDCKOUT,SDTRIG as AF
Touch sensing controller
8 Groups of
3 channels max as AF
VOUT, VINM, VINP
LCD 8x40
LPUART1
SWPMI1
LPTIM1
LPTIM2
SEGx, COMx as AF
RX, TX, CTS, RTS as AF
IO
RX, TX, SUSPEND as AF
IN1, IN2, OUT, ETR as AF
IN1, OUT, ETR as AF
RC HSI
RC LSI
PLL 1&2&3
MSI
Quad SPI memory interface
BK1_IO[3:0]
CLK
NCS
@ VDDUSB
COMP1
INP, INM, OUT
COMP2
INP, INM, OUT
@ VDDA
RTC_OUT
FIFO
PHY
AHB1 80 MHz
CRC
I2C2/SMBUS
I2C3/SMBUS
bxCAN1
OpAmp1
SP3
SP2
UART5
UART4
LCD Booster
V
LCD
V
LCD
= 2.5V to 3.6V
APB2 80MHz
AHB2 80 MHz
OpAmp2
@VDDA
Firewall
VREF Buffer
@ VDDA
@ VDD
DP
DM
SCL, SDA, INTN, ID, VBUS, SOF
VDD = 1.71 to 3.6 V
VSS
VDDA, VSSA
VDD, VSS, NRST
VDDIO2, VDDUSB
VOUT, VINM, VINP
TRACECLK
TRACED[3:0]
NJTRST, JTDI,
JTCK/SWCLK
JTDO/SWD, JTDO
VDD12 = 1.05 to 1.32 V
(1)
VDD12
1. Only available when using external SMPS supply mode.
DAC1
Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.