Datasheet

STM32L476xx Functional overview
DS10198 Rev 8 27/270
Stop 2 LPR No Off ON
LSE
LSI
BOR, PVD, PVM
RTC, LCD, IWDG
COMPx (x=1..2)
I2C3
(10)
LPUART1
(9)
LPTIM1
***
All other peripherals are
frozen.
Reset pin, all I/Os
BOR, PVD, PVM
RTC, LCD, IWDG
COMPx (x=1..2)
I2C3
(10)
LPUART1
(9)
LPTIM1
1.1 µA w/o RTC
1.4 µA w/RTC
5 µs in SRAM
7 µs in Flash
Standby
LPR
Powered
Off
Off
SRAM2
ON
LSE
LSI
BOR, RTC, IWDG
***
All other peripherals are
powered off.
***
I/O configuration can be
floating, pull-up or pull-down
Reset pin
5 I/Os (WKUPx)
(13)
BOR, RTC, IWDG
0.35 µA w/o RTC
0.65 µA w/ RTC
14 µs
OFF
Powered
Off
0.12 µA w/o RTC
0.42 µA w/ RTC
Shutdown OFF
Powered
Off
Off
Powered
Off
LSE
RTC
***
All other peripherals are
powered off.
***
I/O configuration can be
floating, pull-up or pull-
down
(14)
Reset pin
5 I/Os (WKUPx)
(13)
RTC
0.03 µA w/o RTC
0.33 µA w/ RTC
256 µs
1. LPR means Main regulator is OFF and Low-power regulator is ON. 2. All peripherals can be active or clock gated to save power consumption. 3. Typical current at V
DD
= 1.8 V, 25°C. Consumptions values provided running from SRAM, Flash memory Off, 80 MHz in Range 1, 26 MHz in Range 2, 2 MHz in
LPRun/LPSleep.
4. The Flash memory can be put in power-down and its clock can be gated off when executing from SRAM. 5. Theoretical value based on V
DD
= 3.3 V, DC/DC Efficiency of 85%, V
CORE
= 1.10 V
6. Theoretical value based on V
DD
= 3.3 V, DC/DC Efficiency of 85%, V
CORE
= 1.05 V
7. The SRAM1 and SRAM2 clocks can be gated on or off independently.
Table 4. STM32L476xx modes overview (continued)
Mode
Regulator
(1)
CPU Flash SRAM Clocks DMA & Peripherals
(2)
Wakeup source Consumption
(3)
Wakeup time
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