Datasheet
STM32L476xx Pinouts and pin description
DS10198 Rev 8 91/270
62 61 E8 D7 E8 96 B3 B3 140 139 C4 PB9 I/O FT_fl -
IR_OUT, TIM4_CH4,
I2C1_SDA, SPI2_NSS,
DFSDM1_CKIN6,
CAN1_TX, LCD_COM3,
SDMMC1_D5,
SAI1_FS_A, TIM17_CH1,
EVENTOUT
-
- - - - - 97 C3 C3 141 140 A2 PE0 I/O FT_l -
TIM4_ETR, LCD_SEG36,
FMC_NBL0, TIM16_CH1,
EVENTOUT
-
- - - - - 98 A2 A2 142 141 B4 PE1 I/O FT_l -
LCD_SEG37,
FMC_NBL1, TIM17_CH1,
EVENTOUT
-
- 62 - J1 - - - C6 - 142 - VDD12 S - - - -
63 63 A8 A8 A8 99 D3 D3 143 143 M1 VSS S - - - -
64 64 A9 A9 A9 100 C4 C4 144 144 - VDD S - - - -
1. PC13, PC14 and PC15 are supplied through the power switch. Since the switch only sinks a limited amount of current (3 mA), the use of GPIOs PC13 to
PC15 in output mode is limited:
- The speed should not exceed 2 MHz with a maximum load of 30 pF
- These GPIOs must not be used as current sources (e.g. to drive an LED).
2. After a Backup domain power-up, PC13, PC14 and PC15 operate as GPIOs. Their function then depends on the content of the RTC registers which are not
reset by the system reset. For details on how to manage these GPIOs, refer to the Backup domain and RTC register descriptions in the RM0351 reference
manual.
3. OPAMPx_VINM pins are not available as additional functions on pins PA1 and PA7 on UFBGA packages. On UFBGA packages, use the OPAMPx_VINM
dedicated pins.
4. After reset, these pins are configured as JTAG/SW debug alternate functions, and the internal pull-up on PA15, PA13, PB4 pins and the internal pull-down
on PA14 pin are activated.
Table 16. STM32L476xx pin definitions (continued)
Pin Number
Pin name
(function
after
reset)
Pin type
I/O structure
Notes
Pin functions
LQFP64
LQFP64_SMPS
WLCSP72
WLCSP72_SMPS
WLCSP81
LQFP100
UFBGA132
UFBGA132_SMPS
LQFP144
LQFP144_SMPS
UFBGA144
Alternate functions Additional functions
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