Datasheet

ManualsBrandsST ManualsEmbedded Processors & ControllersMicrocontroller 8bit 8KB SOP

This is information on a product in full production.

September 2018 DS12167 Rev 4 1/94

STM8L050J3

Value line, 8-bit ultra-low-power MCU, 8-Kbyte Flash, 256-byte data

EEPROM, RTC, timers, USART, I2C, SPI, ADC, comparators

Datasheet - production data

Features

• Operating conditions

– Operating power supply: 1.8 V to 3.6 V

Temperature range: −40 °C to 125 °C

• Low-power features

– 5 low-power modes: Wait, Low-power run

(5.1 µA), Low-power wait (3 µA), Active-

halt with RTC (1.3 µA), Halt (350 nA)

– Ultra-low leakage per I/O: 50 nA

– Fast wakeup from Halt: 5 µs

• Advanced STM8 core

– Harvard architecture and 3-stage pipeline

– Max freq: 16 MHz, 16 CISC MIPS peak

– Up to 6 external interrupt sources

• Reset and supply management

– Low power, ultra-safe BOR reset with 5

selectable thresholds

– Ultra-low power POR/PDR

– Programmable voltage detector (PVD)

• Clock management

– 32 kHz and 1 to 16 MHz crystal oscillators

– Internal 16 MHz factory-trimmed RC

– Internal 38 kHz low consumption RC

– Clock security system

• Low-power RTC

– BCD calendar with alarm interrupt

– Digital calibration with +/- 0.5 ppm accuracy

– LSE security system

– Auto-wakeup from Halt w/ periodic interrupt

• Memories

– 8 Kbytes of Flash program memory and

256 bytes of data EEPROM with ECC

– Flexible write and read protection modes

– 1 Kbyte of RAM

• DMA

– 4 channels supporting ADC, SPI, I2C,

USART, timers

– 1 channel for memory-to-memory

• 12-bit ADC up to 1 Msps/4 channels

– Internal reference voltage

• Timers

– Two 16-bit timers with 2 channels (used as

IC, OC, PWM), quadrature encoder

– One 8-bit timer with 7-bit prescaler

– 2 watchdogs: 1 Window, 1 Independent

– Beeper timer with 1, 2 or 4 kHz frequencies

• Communication interfaces

– Synchronous serial interface (SPI)

– Fast I2C 400 kHz

SMBus and PMBus

–USART

• Up to 6 I/Os, all mappable on interrupt vectors

• Development support

– Fast on-chip programming and non-

intrusive debugging with SWIM

– Bootloader using USART

• Two ultra-low-power comparators

– One with fixed threshold and another one

with rail to rail

• Wakeup capability

SO8N (4.9x6 mm or 150 mils width)

www.st.com

Downloaded from Arrow.com.

Summary of content (94 pages)

PAGE 1
STM8L050J3 Value line, 8-bit ultra-low-power MCU, 8-Kbyte Flash, 256-byte data EEPROM, RTC, timers, USART, I2C, SPI, ADC, comparators Datasheet - production data Features • Operating conditions – Operating power supply: 1.8 V to 3.6 V Temperature range: −40 °C to 125 °C • Low-power features – 5 low-power modes: Wait, Low-power run (5.1 µA), Low-power wait (3 µA), Activehalt with RTC (1.
PAGE 2
Contents STM8L050J3 Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3 2.1 Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.2 Ultra-low-power continuum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Functional overview . . .
PAGE 3
STM8L050J3 4 3.15 Infrared (IR) interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.16 Development support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.1 5 Contents System configuration options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Memory and register map . . . . . . . . . . . .
PAGE 4
Contents STM8L050J3 9.1 ECOPACK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 9.2 SO8N package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 9.3 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 10 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 11 Revision history . . . . . . . . . . . . . . . . . .
PAGE 5
STM8L050J3 List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. Table 45. Table 46. Table 47.
PAGE 6
List of tables Table 48. Table 49. Table 50. Table 51. Table 52. Table 53. Table 54. Table 55. 6/94 Downloaded from Arrow.com. STM8L050J3 RAIN max for fADC = 16 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 EMS data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 EMI data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PAGE 7
STM8L050J3 List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. STM8L050J3 block diagram . . . . . . . . . . . . . . . . . . . . . .
PAGE 8
Introduction 1 STM8L050J3 Introduction This document describes the features, pinout, mechanical data and ordering information for the STM8L050J3 microcontroller with 8-Kbyte Flash memory. For further details on the STMicroelectronics low density family please refer to Section 2.2: Ultra-low-power continuum.
PAGE 9
STM8L050J3 2 Description Description STM8L050J3 is member of the STM8L ultra-low-power 8-bit family. STM8L050J3 features an enhanced STM8 CPU core providing increased processing power (up to 16 MIPS at 16 MHz) while maintaining the advantages of a CISC architecture with improved code density, a 24-bit linear addressing space and an optimized architecture for low-power operations.
PAGE 10
Description 2.1 STM8L050J3 Device overview Table 1.
PAGE 11
STM8L050J3 2.2 Description Ultra-low-power continuum STM8L050J3 is part of STM8’s ultra-low-power value line on which all the devices are software and feature compatible. Besides the full compatibility within the STM8L family, the devices are part of STMicroelectronics microcontrollers ultra-low-power strategy which also includes the STM8L001xx, STM8L101xx and STM32L15xxx devices. The STM8L and STM32L families allow a continuum of performance, peripherals, system architecture, and features.
PAGE 12
Functional overview 3 STM8L050J3 Functional overview Figure 1 presents the basic block diagram which includes all the functional blocks for STM8L050J3. Figure 1. STM8L050J3 block diagram OSC_IN, OSC_OUT 16 MHz internal RC OSC32_IN, OSC32_OUT @V DD 1-16 MHz oscillator 32 kHz oscillator VDD18 Clock controller and CSS Power VOLT. REG. Clocks to core and peripherals 38 kHz internal RC V DD=1.8 V to 3.
PAGE 13
STM8L050J3 Functional overview WWDG: Window watchdog 3.1 Low-power modes STM8L050J3 as well as all the low density value line STM8L05xxx devices support five lowpower modes to achieve the best compromise between low power consumption, short startup time and available wakeup sources: • Wait mode: The CPU clock is stopped, but selected peripherals keep running. An internal or external interrupt or a Reset can be used to exit the microcontroller from Wait mode (WFE or WFI mode).
PAGE 14
Functional overview 3.2 STM8L050J3 Central processing unit STM8 The central processing unit represents the core of the microcontroller; it executes code and controls the peripherals. 3.2.1 Advanced STM8 Core The 8-bit STM8 core is designed for code efficiency and performance with an Harvard architecture and a 3-stage pipeline.
PAGE 15
STM8L050J3 3.3 Functional overview Reset and supply management The power supplies requirements must be defined in order to have a correct microcontroller operation. The reset and supply management controls the microcontroller operation under defined conditions. 3.3.1 Power supply scheme The device requires a 1.8 V to 3.6 V operating supply voltage (VDD). The external power supply pins must be connected as follows: 3.3.2 • VSS1; VDD1 = 1.8 to 3.
PAGE 16
Functional overview 3.4 STM8L050J3 Clock management The clock controller distributes the system clock (SYSCLK) coming from different oscillators to the core and the peripherals. It also manages clock gating for low-power modes and ensures clock robustness. Features 16/94 Downloaded from Arrow.com. • Clock prescaler: to get the best compromise between speed and current consumption the clock frequency to the CPU and peripherals can be adjusted by a programmable prescaler.
PAGE 17
STM8L050J3 Functional overview Figure 2. STM8L050J3 clock tree diagram SWIM[3:0] OSC_OUT OSC_IN HSE OSC 1-16 MHz HSE HSI HSI RC 1-16 MHz LSI SYSCLK prescaler /1;2;4;8;16;32;64 LSE SYSCLK to core and memory PCLK to peripherals Peripheral Clock enable (13 bits) LSE BEEPCLK CLKBEEPSEL[1:0] LSI LSI RC 38 kHz IWDGCLK to BEEP to IWDG RTCSEL[3:0] OSC32_OUT OSC32_IN CCO RTC prescaler /1;2;4;8;16;32;64 LSE OSC 32.
PAGE 18
Functional overview 3.5 STM8L050J3 Low power real-time clock The real-time clock (RTC) is an independent binary coded decimal (BCD) timer/counter. Six byte locations contain the second, minute, hour (12/24 hour), week day, date, month, year, in BCD (binary coded decimal) format. Correction for 28, 29 (leap year), 30, and 31 day months are made automatically. It provides a programmable alarm and programmable periodic interrupts with wakeup from Halt capability. 3.6 • Periodic wakeup time using the 32.
PAGE 19
STM8L050J3 Functional overview Only the “connect on-the-fly” method can be used to program the device through the SWIM interface. The “connect under-reset” method cannot be used because the NRST pin is not available on this device. The “connect on-the-fly” mode can be used while the device is executing code, but if there is a device reset (by software reset) during the SWIM connection, this connection is aborted and it must be performed again from the debug tool.
PAGE 20
Functional overview 3.10 STM8L050J3 System configuration controller and routing interface The system configuration controller provides the capability to remap some alternate functions on different I/O ports. TIM4 and ADC1 DMA channels can also be remapped. The highly flexible routing interface controls the routing of internal analog signals to ADC1 and the internal reference voltage VREFINT. 3.
PAGE 21
STM8L050J3 3.12.1 Functional overview Window watchdog timer The window watchdog (WWDG) is used to detect the occurrence of a software fault, usually generated by external interferences or by unexpected logical conditions, which cause the application program to abandon its normal sequence. 3.12.2 Independent watchdog timer The independent watchdog peripheral (IWDG) can be used to resolve processor malfunctions due to hardware or software failures.
PAGE 22
Functional overview 3.14.3 STM8L050J3 USART The USART interface (USART1) allows full duplex, asynchronous communications with external devices requiring an industry standard NRZ asynchronous serial data format. It offers a very wide range of baud rates. • 1 Mbit/s full duplex SCI • SPI emulation • High precision baud rate generator • Smartcard emulation • IrDA SIR encoder decoder • Single wire half duplex mode Note: USART1 can be served by the DMA1 Controller. 3.
PAGE 23
STM8L050J3 Functional overview Recommendations for SWIM pin (pin#1) sharing If the SWIM pin should be used with the I/O pin functionality, it is recommended to add a ~5 seconds delay in the firmware before changing the functionality on the pin with SWIM functions. This action allows the user to set the device into SWIM mode after the device power on and to be able to reprogram the device.
PAGE 24
Pin description 4 STM8L050J3 Pin description This section describes the device’s pin functions (see Table 4) and package’s pinout (see Figure 3). Figure 3.
PAGE 25
STM8L050J3 Pin description Table 4.
PAGE 26
Pin description STM8L050J3 Table 4. STM8L050J3 pin description (continued) 8 - X - T(5) - PP High sink/source X OD Ext.
PAGE 27
STM8L050J3 4.1 Pin description System configuration options As shown in Table 4: STM8L050J3 pin description, some functions can be remapped on different I/O ports by programming one of the two remapping registers described in the “Routing interface (RI) and system configuration controller” section in the STM8L050J3, STM8L051F3, STM8L052C6, STM8L052R8 MCUs and STM8L151/L152, STM8L162, STM8AL31, STM8AL3L lines reference manual (RM0031). DS12167 Rev 4 27/94 43 Downloaded from Arrow.com.
PAGE 28
Memory and register map 5 STM8L050J3 Memory and register map The following sections describe the mapping of the device’s memory and peripherals. 5.1 Memory mapping The memory map is shown in Figure 4. Figure 4.
PAGE 29
STM8L050J3 Memory and register map address. 2. Refer to Table 7 for an overview of hardware register mapping, to Table 6 for details on I/O port hardware registers, and to Table 8 for information on CPU/SWIM/debug module controller registers. Table 5. Flash and RAM boundary addresses Memory area Size Start address End address RAM 1 Kbyte 0x00 0000 0x00 03FF Flash program memory 8 Kbytes 0x00 8000 0x00 9FFF 5.2 Register map Table 6.
PAGE 30
Memory and register map STM8L050J3 Table 7.
PAGE 31
STM8L050J3 Memory and register map Table 7.
PAGE 32
Memory and register map STM8L050J3 Table 7.
PAGE 33
STM8L050J3 Memory and register map Table 7.
PAGE 34
Memory and register map STM8L050J3 Table 7.
PAGE 35
STM8L050J3 Memory and register map Table 7.
PAGE 36
Memory and register map STM8L050J3 Table 7.
PAGE 37
STM8L050J3 Memory and register map Table 7.
PAGE 38
Memory and register map STM8L050J3 Table 7.
PAGE 39
STM8L050J3 Memory and register map Table 7.
PAGE 40
Memory and register map STM8L050J3 Table 8.
PAGE 41
STM8L050J3 Memory and register map Table 8. CPU/SWIM/debug module/interrupt controller registers (continued) Address Block 0x00 7F97 0x00 7F98 0x00 7F99 DM 0x00 7F9A 0x00 7F9B to 0x00 7F9F Register label Register name Reset status DM_CR2 DM Debug module control register 2 0x00 DM_CSR1 DM Debug module control/status register 1 0x10 DM_CSR2 DM Debug module control/status register 2 0x00 DM_ENFCTR DM enable function register 0xFF Reserved area (5 bytes) 1.
PAGE 42
Interrupt vector mapping 6 STM8L050J3 Interrupt vector mapping The interrupt vector mapping is described in Table 9. I IRQ No. Table 9.
PAGE 43
STM8L050J3 Interrupt vector mapping Table 9.
PAGE 44
Option bytes 7 STM8L050J3 Option bytes Option bytes contain configurations for device hardware features as well as the memory protection of the device. They are stored in a dedicated memory block. All option bytes can be modified in ICP mode (with SWIM) by accessing the EEPROM address. See Table 10 for details on option byte addresses.
PAGE 45
STM8L050J3 Option bytes Table 11. Option byte description Option byte No. Option description OPT0 ROP[7:0] Memory readout protection (ROP) 0xAA: Disable readout protection (write access via SWIM protocol) Refer to the “Readout protection” section in the STM8L050J3, STM8L051F3, STM8L052C6, STM8L052R8 MCUs and STM8L151/L152, STM8L162, STM8AL31, STM8AL3L lines reference manual (RM0031). OPT1 UBC[7:0] Size of the user boot code area 0x00: UBC is not protected. 0x01: Page 0 is write protected.
PAGE 46
Option bytes STM8L050J3 Table 11. Option byte description (continued) Option byte No. OPT5 Option description BOR_ON: 0: Brownout reset off 1: Brownout reset on BOR_TH[3:1]: Brownout reset thresholds. Refer to Table 20 for details on the thresholds according to the value of BOR_TH bits. OPTBL 46/94 Downloaded from Arrow.com. OPTBL[15:0]: This option is checked by the boot ROM code after reset.
PAGE 47
STM8L050J3 8 Electrical parameters Electrical parameters This section describes the quantification of the given device’s parameters. 8.1 Parameter conditions Unless otherwise specified, all voltages are referred to VSS. 8.1.
PAGE 48
Electrical parameters 8.1.5 STM8L050J3 Pin input voltage The input voltage measurement on a pin of the device is described in Figure 6. Figure 6. Pin input voltage STM8 PIN VIN MSv37775V1 8.2 Absolute maximum ratings Stresses above the absolute maximum ratings listed in Table 12: Voltage characteristics, Table 13: Current characteristics, and Table 14: Thermal characteristics may cause permanent damage to the device.
PAGE 49
STM8L050J3 Electrical parameters Table 13. Current characteristics Symbol Ratings Max. IVDD Total current into VDD power line (source) 80 IVSS Total current out of VSS ground line (sink) 80 Output current sunk by IR_TIM pin (with high sink LED driver capability) 80 Output current sunk by any other I/O and control pin 25 IIO Output current sourced by any I/Os and control pin IINJ(PIN) ΣIINJ(PIN) 1.
PAGE 50
Electrical parameters 8.3 STM8L050J3 Operating conditions Subject to general operating conditions for VDD and TA. 8.3.1 General operating conditions The operating conditions define the conditions under which the device operates correctly according to its specification (see Table 15). Table 15. General operating conditions Symbol fSYSCLK(1) Parameter System clock frequency Conditions Min. Max. Unit 1.8 V ≤ VDD < 3.6 V 0 16 MHz - 1.8 3.6 V Must be at the same potential as VDD 1.8 3.
PAGE 51
STM8L050J3 8.3.2 Electrical parameters Embedded reset and power control block characteristics The reset and power block parameters are described in Table 16 and are derived from tests performed under the ambient temperature conditions summarized in Table 15: General operating conditions. Table 16.
PAGE 52
Electrical parameters STM8L050J3 Figure 7. POR/BOR thresholds VDD VDD 3.6 V Operatin g power supply V DD BOR threshold_0 1.8 V BOR threshold VBOR0 VPDR PDR threshold Reset Safe reset Safe reset release without BOR = battery life extension Internal NRST with BOR with without BOR BOR Time BOR always active at power up BOR activated by user for power-down detection ai17033b 8.3.
PAGE 53
STM8L050J3 Electrical parameters Table 17. Total current consumption in Run mode Symbol Para meter Conditions(1) HSI RC osc. (16 MHz)(3) Supply current IDD(RUN) in run mode(2) All peripherals OFF, code executed HSE external from RAM, clock VDD from (fCPU=fHSE)(4) 1.8 V to 3.6 V Unit 55 °C 85 °C 125 °C fCPU = 125 kHz 0.39 0.47 0.49 0.55 fCPU = 1 MHz 0.48 0.56 0.58 0.65 fCPU = 4 MHz 0.75 0.84 0.86 0.99 fCPU = 8 MHz 1.10 1.20 1.25 1.40 fCPU = 16 MHz 1.85 1.93 2.12(5) 2.
PAGE 54
Electrical parameters STM8L050J3 6. The run from Flash consumption can be approximated with the linear formula: IDD(run_from_Flash) = Freq * 195 µA/MHz + 440 µA 7. Oscillator bypassed (LSEBYP = 1 in CLK_ECKCR). When configured for extenal crystal, the LSE consumption (IDD LSE) must be added. Refer to Table 29. Figure 8. Typ. IDD(RUN) vs. VDD, fCPU = 16 MHz 3.00 -40°C IDD(RUN)HSI [mA] 2.75 25°C 85°C 2.50 2.25 2.00 1.75 1.50 1.8 2.1 2.6 3.1 3.6 VDD [V] ai18213b 1.
PAGE 55
STM8L050J3 Electrical parameters In the following table, data is based on characterization results, unless otherwise specified. Table 18. Total current consumption in Wait mode Max Symbol Conditions(1) Parameter Supply IDD(Wait) current in Wait mode Supply current in IDD(Wait) Wait mode 85°C 125°C 0.33 0.39 0.41 0.45 fCPU = 1 MHz 0.35 0.41 0.44 0.48 fCPU = 4 MHz 0.42 0.51 0.52 0.58 fCPU = 8 MHz 0.52 0.57 0.58 0.62 fCPU = 16 MHz 0.68 0.76 0.79 0.85 fCPU = 125 kHz 0.032 0.
PAGE 56
Electrical parameters STM8L050J3 4. Oscillator bypassed (LSEBYP = 1 in CLK_ECKCR). When configured for external crystal, the LSE consumption (IDD HSE) must be added. Refer to Table 29. 5. Oscillator bypassed (LSEBYP = 1 in CLK_ECKCR). When configured for external crystal, the LSE consumption (IDD HSE) must be added. Refer to Table 29. Figure 9. Typ. IDD(Wait) vs. VDD, fCPU = 16 MHz 1) 1000 950 IDD(WAIT)HSI [μA] 900 850 800 750 700 -40°C 650 25°C 600 85°C 550 500 1.8 2.1 2.6 3.1 VDD [V] 1.
PAGE 57
STM8L050J3 Electrical parameters In the following table, data is based on characterization results, unless otherwise specified. Table 19. Total current consumption and timing in Low-power run mode at VDD = 1.8 V to 3.6 V Symbol Conditions(1) Parameter all peripherals OFF LSI RC osc. (at 38 kHz) with TIM2 active(2) IDD(LPR) Supply current in Low-power run mode all peripherals OFF LSE (3) external clock (32.768 kHz) with TIM2 active (2) Typ Max Unit TA = -40 °C to 25 °C 5.1 5.4 TA = 55 °C 5.
PAGE 58
Electrical parameters STM8L050J3 In the following table, data is based on characterization results, unless otherwise specified. Table 20. Total current consumption in Low-power wait mode at VDD = 1.8 V to 3.6 V Symbol Conditions(1) Parameter Typ Max Unit TA = -40 °C to 25 °C all peripherals OFF LSI RC osc. (at 38 kHz) with TIM2 active(2) IDD(LPW) Supply current in Low-power wait mode all peripherals OFF LSE external clock(3) (32.768 kHz) with TIM2 active (2) 3 3.3 TA = 55 °C 3.3 3.
PAGE 59
STM8L050J3 Electrical parameters In the following table, data is based on characterization results, unless otherwise specified. Table 21. Total current consumption and timing in Active-halt mode at VDD = 1.8 V to 3.6 V Symbol Conditions (1) Parameter Typ Max TA = -40 °C to 25 °C 0.9 2.1 TA = 55 °C 1.2 3 TA = 85 °C 1.5 3.4 TA = 125 °C 5.1 12 TA = -40 °C to 25 °C 0.5 1.2 TA = 55 °C 0.62 1.4 TA = 85 °C 0.88 2.1 TA = 125 °C 4.8 11 - - 2.
PAGE 60
Electrical parameters STM8L050J3 In the following table, data is based on characterization results, unless otherwise specified. Table 23. Total current consumption and timing in Halt mode at VDD = 1.8 to 3.6 V Symbol Condition(1) Parameter Typ Max 350 1400(2) 580 2000 1160 2800(2) TA = 125 °C 4.
PAGE 61
STM8L050J3 Electrical parameters Current consumption of on-chip peripherals Table 24. Peripheral current consumption Symbol Typ. VDD = 3.
PAGE 62
Electrical parameters STM8L050J3 Table 25. Current consumption under external reset Symbol IDD(RST) Parameter Conditions Supply current under external reset (1) All pins are externally tied to VDD Typ VDD = 1.8 V 48 VDD = 3 V 76 VDD = 3.6 V 91 Unit µA 1. All pins except PA0, PB0 and PB4 are floating under reset. PA0, PB0 and PB4 are configured with pull-up under reset. 8.3.
PAGE 63
STM8L050J3 Electrical parameters HSE crystal/ceramic resonator oscillator The HSE clock can be supplied with a 1 to 16 MHz crystal/ceramic resonator oscillator. All the information given in this paragraph is based on characterization results with specified typical external components. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time.
PAGE 64
Electrical parameters STM8L050J3 LSE crystal/ceramic resonator oscillator The LSE clock can be supplied with a 32.768 kHz crystal/ceramic resonator oscillator. All the information given in this paragraph is based on characterization results with specified typical external components. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time.
PAGE 65
STM8L050J3 Electrical parameters Internal clock sources Subject to general operating conditions for VDD, and TA. High speed internal RC oscillator (HSI) In the following table, data is based on characterization results, not tested in production, unless otherwise specified. Table 30. HSI oscillator characteristics Symbol fHSI Conditions(1) Parameter Min Typ Max Unit - 16 - MHz -2.5 - 2.5 % 1.8 V ≤ VDD ≤ 3.6 V, -40 °C ≤ TA ≤ 125 °C -5 - 5 % Trimming code ≠ multiple of 16 - 0.4 0.
PAGE 66
Electrical parameters STM8L050J3 Low speed internal RC oscillator (LSI) In the following table, data is based on characterization results, not tested in production. Table 31. LSI oscillator characteristics Parameter (1) Symbol fLSI Conditions(1) Min Typ Max Unit - 26 38 56 kHz Frequency tsu(LSI) LSI oscillator wakeup time IDD(LSI) LSI oscillator frequency drift(3) 0 °C ≤TA ≤ 85 °C (2) - - 200 -12 - 11 µs % 1. VDD = 1.8 V to 3.6 V, TA = -40 to 125 °C unless otherwise specified. 2.
PAGE 67
STM8L050J3 8.3.5 Electrical parameters Memory characteristics TA = -40 to 125 °C unless otherwise specified. Table 32. RAM and hardware registers Symbol Parameter Conditions Min Typ Max Unit VRM Data retention mode (1) Halt mode (or Reset) 1.8 - - V 1. Minimum supply voltage without losing data stored in RAM (in Halt mode or under Reset) or in hardware registers (only in Halt mode). Guaranteed by characterization. Flash memory Table 33.
PAGE 68
Electrical parameters 8.3.6 STM8L050J3 I/O current injection characteristics As a general rule, current injection to the I/O pins, due to external voltage below VSS or above VDD (for standard pins) should be avoided during normal product operation. However, in order to give an indication of the robustness of the microcontroller in cases when abnormal injection accidentally happens, susceptibility tests are performed on a sample basis during device characterization.
PAGE 69
STM8L050J3 Electrical parameters Table 35. I/O static characteristics Symbol VIL Conditions(1) Min Typ Max Input voltage on true open-drain pins (PC0 and PC1) VSS-0.3 - 0.3 x VDD Input voltage on any other pin VSS-0.3 - 0.3 x VDD 0.70 x VDD - VDD+0.
PAGE 70
Electrical parameters STM8L050J3 Figure 16. Typical VIL and VIH vs VDD (high sink I/Os) 3 -40°C 25°C 2.5 85°C VIL and VIH [V] 2 1.5 1 0.5 0 1.8 2.1 2.6 3.1 3.6 VDD [V] ai18220c Figure 17. Typical VIL and VIH vs VDD (true open drain I/Os) 3 -40°C 25°C 2.5 VIL and VIH [V] 85°C 2 1.5 1 0.5 0 1.8 2.1 2.6 VDD [V] 3.1 3.6 ai18221b 70/94 Downloaded from Arrow.com.
PAGE 71
STM8L050J3 Electrical parameters Figure 18. Typical pull-up resistance RPU vs VDD with VIN=VSS 60 -40°C 55 25°C Pull-up resistance [kΩ] 85°C 50 45 40 35 30 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 VDD [V] ai18222b Figure 19. Typical pull-up current Ipu vs VDD with VIN=VSS 120 -40°C 25°C 100 Pull-up current [μA] 85°C 80 60 40 20 0 1.8 1.95 2.1 2.25 2.4 2.55 2.7 2.85 3 3.15 3.3 3.45 3.6 VDD [V] ai18223b DS12167 Rev 4 71/94 87 Downloaded from Arrow.com.
PAGE 72
Electrical parameters STM8L050J3 Output driving current Subject to general operating conditions for VDD and TA unless otherwise specified. Table 36. Output driving current (high sink ports) I/O Symbol Type Output low level voltage for an I/O pin High sink VOL (1) Parameter VOH (2) Output high level voltage for an I/O pin Conditions Min Max Unit IIO = +2 mA, VDD = 3.0 V - 0.45 V IIO = +2 mA, VDD = 1.8 V - 0.45 V IIO = +10 mA, VDD = 3.0 V - 0.7 V IIO = -2 mA, VDD = 3.0 V VDD-0.
PAGE 73
STM8L050J3 Electrical parameters Figure 20. Typ. VOL @ VDD = 3.0 V (high sink ports) Figure 21. Typ. VOL @ VDD = 1.8 V (high sink ports) 1 0.7 -40°C 25°C 85°C 0.6 -40°C 25°C 85°C 0.5 VOL [V] VOL [V] 0.75 0.5 0.25 0.4 0.3 0.2 0.1 0 0 2 4 6 8 10 12 14 16 18 0 20 0 IOL [mA] 1 2 3 4 ai18226V2 Figure 22. Typ. VOL @ VDD = 3.0 V (true open drain ports) 5 6 7 IOL [mA] Figure 23. Typ. VOL @ VDD = 1.8 V (true open drain ports) 0.5 0.5 -40°C 25°C 85°C 0.4 0.
PAGE 74
Electrical parameters 8.3.8 STM8L050J3 Communication interfaces SPI1 - Serial peripheral interface Unless otherwise specified, the parameters given in Table 39 are derived from tests performed under ambient temperature, fSYSCLK frequency and VDD supply voltage conditions summarized in Section 8.3.1. Refer to I/O port characteristics for more details on the input/output alternate function characteristics (NSS, SCK, MOSI, MISO). Table 39.
PAGE 75
STM8L050J3 Electrical parameters Figure 26. SPI1 timing diagram - slave mode and CPHA=0 Figure 27. SPI1 timing diagram - slave mode and CPHA=1(1) NSS input SCK input tSU(NSS) CPHA=1 CPOL=0 CPHA=1 CPOL=1 tw(SCKH) tw(SCKL) th(SO) tv(SO) ta(SO) MISO OUTPUT MSB OUT BIT6 OUT tr(SCK) tf(SCK) tdis(SO) LSB OUT th(SI) tsu(SI) MOSI INPUT th(NSS) tc(SCK) MSB IN BIT 1 IN LSB IN ai14135b 1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD. DS12167 Rev 4 75/94 87 Downloaded from Arrow.
PAGE 76
Electrical parameters STM8L050J3 Figure 28. SPI1 timing diagram - master mode(1) 1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD. 76/94 Downloaded from Arrow.com.
PAGE 77
STM8L050J3 Electrical parameters I2C - Inter IC control interface Subject to general operating conditions for VDD, fSYSCLK, and TA unless otherwise specified. The STM8L I2C interface (I2C1) meets the requirements of the Standard I2C communication protocol described in the following table with the restriction mentioned below: Refer to I/O port characteristics for more details on the input/output alternate function characteristics (SDA and SCL). Table 40.
PAGE 78
Electrical parameters STM8L050J3 Figure 29. Typical application with I2C bus and timing diagram 1) 1. Measurement points are done at CMOS levels: 0.3 x VDD and 0.7 x VDD 78/94 Downloaded from Arrow.com.
PAGE 79
STM8L050J3 8.3.9 Electrical parameters Embedded reference voltage In the following table, data is based on characterization results, not tested in production, unless otherwise specified. Table 41. Reference voltage characteristics Symbol Parameter Conditions Min Typ Max. Unit Internal reference voltage consumption - - 1.4 - µA ADC sampling time when reading the internal reference voltage - - 5 10 µs Internal reference voltage buffer consumption (used for ADC) - - 13.
PAGE 80
Electrical parameters STM8L050J3 Table 42. Comparator 1 characteristics Min Typ Max(1) Unit Analog supply voltage 1.65 - 3.6 V Temperature range -40 - 125 °C R400K R400K value 300 400 500 R10K R10K value 7.5 10 12.5 0.6 - VDDA 1.202 1.224 1.
PAGE 81
STM8L050J3 8.3.11 Electrical parameters 12-bit ADC1 characteristics In the following table, data is guaranteed by design, not tested in production. Table 44. ADC1 characteristics Symbol Parameter VDDA Analog supply voltage VREF+ Reference supply voltage VREFIVDDA IVREF+ Conditions 2.4 V ≤ VDDA ≤ 3.6 V Min Typ Max Unit 1.8 - 3.6 V 2.4 - VDDA V 1.8 V ≤ VDDA ≤ 2.
PAGE 82
Electrical parameters STM8L050J3 Table 44. ADC1 characteristics (continued) Symbol Parameter Conditions Min Typ Max Unit tIDLE Time before a new conversion - - - ∞ ms tVREFINT Internal reference voltage startup time - - - refer to Table 41 ms 1. The current consumption through VREF is composed of two parameters: - one constant (max 300 µA) - one variable (max 400 µA), only during sampling time + 2 first conversion pulses.
PAGE 83
STM8L050J3 Electrical parameters In the following three tables, data is guaranteed by characterization result, not tested in production. Table 45. ADC1 accuracy with VDDA = 3.3 V to 2.5 V Symbol Parameter Conditions Typ Max 1 1.6 Differential non linearity fADC = 8 MHz 1 1.6 fADC = 4 MHz 1 1.5 fADC = 16 MHz 1.2 2 fADC = 8 MHz 1.2 1.8 fADC = 4 MHz 1.2 1.7 fADC = 16 MHz 2.2 3.0 fADC = 8 MHz 1.8 2.5 fADC = 4 MHz 1.8 2.3 fADC = 16 MHz 1.5 2 fADC = 8 MHz 1 1.
PAGE 84
Electrical parameters STM8L050J3 Figure 30. ADC1 accuracy characteristics Figure 31. Typical connection diagram using the ADC STM8 VDD Sample and hold ADC converter VT 0.6V (1) RAIN Cparasitic (2) VAIN RADC AINx VT 0.6V 12-bit converter CADC(1) I L± 50nA ai17090f 1. Refer to Table 48 for the values of RAIN and CADC. 2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the pad capacitance (roughly 7 pF).
PAGE 85
STM8L050J3 Electrical parameters Table 48. RAIN max for fADC = 16 MHz(1) RAIN max (kohm) Ts (cycles) Ts (µs) Slow channels 2.4 V < VDDA < 3.6 V 1.8 V < VDDA < 2.4 V 4 0.25 Not allowed Not allowed 9 0.5625 0.8 Not allowed 16 1 2.0 0.8 24 1.5 3.0 1.8 48 3 6.8 4.0 96 6 15.0 10.0 192 12 32.0 25.0 384 24 50.0 50.0 1. Guaranteed by design. General PCB design guidelines Power supply decoupling should be performed as shown in Figure 33.
PAGE 86
Electrical parameters 8.3.12 STM8L050J3 EMC characteristics Susceptibility tests are performed on a sample basis during product characterization. Functional EMS (electromagnetic susceptibility) Based on a simple running application on the product (toggling 2 LEDs through I/O ports), the product is stressed by two electromagnetic events until a failure occurs (indicated by the LEDs).
PAGE 87
STM8L050J3 Electrical parameters Table 50. EMI data (1) Symbol Parameter SEMI VDD = 3.6 V, TA = +25 °C, SO8N conforming to IEC61967-2 Peak level Monitored frequency band Conditions Max vs. Unit 16 MHz 0.1 MHz to 30 MHz TBD 30 MHz to 130 MHz TBD 130 MHz to 1 GHz TBD SAE EMI Level TBD dBμV - 1. Not tested in production.
PAGE 88
Package characteristics 9 STM8L050J3 Package characteristics Failure analysis and guarantee The small number of pins available induces limitations on failure analysis depth in case of isolated symptoms, typically with an impact lower than 0.1%. Please contact your sales office for additional information for any failure analysis. STMicroelectronics will make a feasibility study for investigation based on failure rate and symptom description prior to responsibility endorsement. 9.
PAGE 89
STM8L050J3 Package characteristics Table 53. SO8N – 8-lead 4.9 x 6 mm, plastic small outline, 150 mils body width, package mechanical data (continued) inches(1) millimeters Symbol Min. Typ. Max. Min. Typ. Max. D 4.800 4.900 5.000 0.1890 0.1929 0.1969 E 5.800 6.000 6.200 0.2283 0.2362 0.2441 E1 3.800 3.900 4.000 0.1496 0.1535 0.1575 e - 1.270 - - 0.0500 - h 0.250 - 0.500 0.0098 - 0.0197 k 0° - 8° 0° - 8° L 0.400 - 1.270 0.0157 - 0.0500 L1 - 1.
PAGE 90
Package characteristics STM8L050J3 Figure 36. Example of SO8N marking (package top view) Product identification 8L050J3 R Y WW Date code Unmarkable surface PIN1 reference Additional information MSv46320V1 1. Parts marked as ES or E or accompanied by an Engineering Sample notification letter are not yet qualified and therefore not approved for use in production. ST is not responsible for any consequences resulting from such use.
PAGE 91
STM8L050J3 9.3 Package characteristics Thermal characteristics The maximum chip junction temperature (TJmax) must never exceed the values given in Table 15: General operating conditions on page 50.
PAGE 92
Ordering information 10 STM8L050J3 Ordering information Figure 37.
PAGE 93
STM8L050J3 11 Revision history Revision history Table 55. Document revision history Date Revision 06-Jun-2017 1 Initial release. 04-Oct-2017 2 Updated: – Document’s classification to “Public” – Section 1: Introduction – Section 3.1: Low-power modes – Section 3.2.2: Interrupt controller – Section 3.3.3: Voltage regulator – Section 3.14.1: SPI – Section 3.14.3: USART – Table 4: STM8L050J3 pin description – Note 3 on page 26 – Section 4.
PAGE 94
STM8L050J3 IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement.