Datasheet
Pin description STM8L050J3
26/94 DS12167 Rev 4
Note: 1 The slope control of all GPIO pins, except true open drain pins, can be programmed. By
default, the slope control is limited to 2 MHz.
2 The PA1, PB0, PB1, PB2 and PB4 should be configured after device reset by user software
into the output push-pull mode with output low-state to reduce the device’s consumption and
to improve its EMC immunity. The GPIOs mentioned above are not connected to pins, and
they are in input-floating mode after a device reset. To configure PA1 pin in output push-pull
mode refer to Section “Configuring NRST/PA1 pin as general purpose output” in the
STM8L050J3, STM8L051F3, STM8L052C6, STM8L052R8 MCUs and STM8L151/L152,
STM8L162, STM8AL31, STM8AL3L lines reference manual (RM0031).
3 As several pins provide a connection to multiple GPIOs, the mode selection for any of those
GPIOs impacts all the other GPIOs connected to the same pin. The user is responsible for
the proper setting of the GPIO modes in order to avoid conflicts between GPIOs bonded to
the same pin (including their alternate functions). For example, pull-up enabled on PA0 is
also seen on PA2 and PC6. Push-pull configuration of PB3 is also seen on PB5 and PD0,
etc.
8
PC1/I2C_SCL I/O - X -X-T
(5)
-
Port
C1
I2C clock
PC4/USART_CK]/
I2C_SMB/CCO/ADC1_IN4/CO
MP1_INP/COMP2_INM
I/O - X XXHSXX
Port
C4
USART synchronous clock /
I2C1_SMB / Configurable clock
output / ADC1_IN4/ Comparator1
positive input/ Comparator2
negative input
PC5/OSC32_IN /[SPI_NSS]
(2)
/
[USART_TX]/TIM2_CH1
I/O - X XXHSXX
Port
C5
LSE oscillator input / [SPI
master/slave select] / [USART
transmit]/Timer 2 -channel 1
1. The PA0 pin is in input pull-up during the reset phase and after reset release. The default PA0 influences all the GPIOs
connected in parallel on pin number 1 (PA2, PC6).
2. [ ] Alternate function remapping option (if the same alternate function is shown twice, it indicates an exclusive choice not a
duplication of the function).
3. High Sink LED driver capability available on PA0.
4. The SPI_MISO signal on PA2 (pin1) cannot be used in application because it is shared with the SPI_SCK signal on the
same pin.
5. In the open-drain output column, ‘T’ defines a true open-drain I/O (P-buffer and protection diode to VDD are not
implemented). Although PC0/PC1 itself is a true open drain GPIO with its respective circuitry and characteristics, the
maximum V
IN
of the pin number 7 and pin number 8 is limited by the standard GPIO (PB7 or PC4/PC5) which is also
bonded to the same pin number.
Table 4. STM8L050J3 pin description (continued)
pin
n°
Pin name
Type
I/O level
Input Output
Main function
(after reset)
Default alternate function
SO8N
floating
wpu
Ext. interrupt
High sink/source
OD
PP
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