Datasheet

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This is information on a product in full production.

September 2018 DS9178 Rev 4 1/96

STM8L051F3

8-bit ultra-low-power MCU, 8-Kbyte Flash memory,

256-byte data EEPROM, RTC, timers, USART, I2C, SPI, ADC

Datasheet - production data

Features

• Operating conditions

– Operating power supply: 1.8 V to 3.6 V

Temperature range: −40 °C to 85 °C

• Low-power features

– 5 low-power modes: Wait, Low-power run

(5.1 µA), Low-power wait (3 µA), Active-

halt with RTC (1.3 µA), Halt (350 nA)

– Ultra-low leakage per I/O: 50 nA

– Fast wakeup from Halt: 5 µs

• Advanced STM8 core

– Harvard architecture and 3-stage pipeline

– Max freq: 16 MHz, 16 CISC MIPS peak

– Up to 40 external interrupt sources

• Reset and supply management

– Low power, ultra-safe BOR reset with 5

selectable thresholds

– Ultra-low power POR/PDR

– Programmable voltage detector (PVD)

• Clock management

– 32 kHz and 1 to 16 MHz crystal oscillators

– Internal 16 MHz factory-trimmed RC

– Internal 38 kHz low consumption RC

– Clock security system

• Low-power RTC

– BCD calendar with alarm interrupt

– Digital calibration with +/- 0.5 ppm accuracy

– LSE security system

– Auto-wakeup from Halt w/ periodic interrupt

• Memories

– 8 Kbytes of Flash program memory and

256 bytes of data EEPROM with ECC

– Flexible write and read protection modes

– 1 Kbyte of RAM

• DMA

– 4 channels supporting ADC, SPI, I2C,

USART, timers

– 1 channel for memory-to-memory

• 12-bit ADC up to 1 Msps/10 channels

– Internal reference voltage

• Timers

– Two 16-bit timers with 2 channels (used as

IC, OC, PWM), quadrature encoder

– One 8-bit timer with 7-bit prescaler

– 2 watchdogs: 1 Window, 1 Independent

– Beeper timer with 1, 2 or 4 kHz frequencies

• Communication interfaces

– Synchronous serial interface (SPI)

– Fast I2C 400 kHz

SMBus and PMBus

–USART

• Up to 18 I/Os, all mappable on interrupt vectors

• Development support

– Fast on-chip programming and non-

intrusive debugging with SWIM

– Bootloader using USART

TSSOP20 ( 6.4x4.4 mm or 169 mils width)

www.st.com

Downloaded from Arrow.com.

Summary of content (96 pages)

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STM8L051F3 8-bit ultra-low-power MCU, 8-Kbyte Flash memory, 256-byte data EEPROM, RTC, timers, USART, I2C, SPI, ADC Datasheet - production data Features • Operating conditions – Operating power supply: 1.8 V to 3.6 V Temperature range: −40 °C to 85 °C • Low-power features – 5 low-power modes: Wait, Low-power run (5.1 µA), Low-power wait (3 µA), Activehalt with RTC (1.
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Contents STM8L051F3 Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3 2.1 Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.2 Ultra-low-power continuum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Functional overview . . .
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STM8L051F3 3.15 4 Development support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.1 5 Contents System configuration options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Memory and register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5.1 Memory mapping . . . . . . . . . . . . . . . . . . . . .
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Contents STM8L051F3 9.3 TSSOP20 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 9.4 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 10 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 11 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 4/96 Downloaded from Arrow.com.
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STM8L051F3 List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. Table 45. Table 46. Table 47.
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List of tables Table 48. Table 49. Table 50. Table 51. Table 52. Table 53. Table 54. 6/96 Downloaded from Arrow.com. STM8L051F3 EMS data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 EMI data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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STM8L051F3 List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40. Figure 41.
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Introduction 1 STM8L051F3 Introduction This document describes the features, pinout, mechanical data and ordering information for the low density STM8L051F3 microcontroller with 8-Kbyte Flash memory density. For further details on the whole STMicroelectronics low density family please refer to Section 2.2: Ultra-low-power continuum.
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STM8L051F3 2 Description Description STM8L051F3 is member of the STM8L ultra-low-power 8-bit family. STM8L051F3 features an enhanced STM8 CPU core providing increased processing power (up to 16 MIPS at 16 MHz) while maintaining the advantages of a CISC architecture with improved code density, a 24-bit linear addressing space and an optimized architecture for low-power operations.
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Description 2.1 STM8L051F3 Device overview Table 1.
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STM8L051F3 2.2 Description Ultra-low-power continuum STM8L051F3 is part of STM8’s ultra-low-power value line on which all the devices are pinto-pin, software and feature compatible. Besides the full compatibility within the STM8L family, the devices are part of STMicroelectronics microcontrollers ultra-low-power strategy which also includes the STM8L001xx, STM8L101xx and STM32L15xxx devices. The STM8L and STM32L families allow a continuum of performance, peripherals, system architecture, and features.
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Functional overview 3 STM8L051F3 Functional overview Figure 1. STM8L051F3 block diagram OSC_IN, OSC_OUT @V DD 1-16 MHz oscillator V DD18 16 MHz internal RC OSC32_IN, OSC32_OUT 32 kHz oscillator Clock controller and CSS Power VOLT. REG. Clocks to core and peripherals 38 kHz internal RC RESET V DD =1.8 V to 3.
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STM8L051F3 3.1 Functional overview Low-power modes STM8L051F3 as well as all the low density value line STM8L05xxx devices support five lowpower modes to achieve the best compromise between low power consumption, short startup time and available wakeup sources: • Wait mode: The CPU clock is stopped, but selected peripherals keep running. An internal or external interrupt or a Reset can be used to exit the microcontroller from Wait mode (WFE or WFI mode).
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Functional overview 3.2 STM8L051F3 Central processing unit STM8 The central processing unit represents the core of the microcontroller; it executes code and controls the peripherals. 3.2.1 Advanced STM8 Core The 8-bit STM8 core is designed for code efficiency and performance with an Harvard architecture and a 3-stage pipeline.
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STM8L051F3 3.3 Functional overview Reset and supply management The power supplies requirements must be defined in order to have a correct microcontroller operation. The reset and supply management controls the microcontroller operation under defined conditions. 3.3.1 Power supply scheme The device requires a 1.8 V to 3.6 V operating supply voltage (VDD). The external power supply pins must be connected as follows: 3.3.2 • VSS1; VDD1 = 1.8 to 3.
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Functional overview 3.4 STM8L051F3 Clock management The clock controller distributes the system clock (SYSCLK) coming from different oscillators to the core and the peripherals. It also manages clock gating for low-power modes and ensures clock robustness. Features 16/96 Downloaded from Arrow.com. • Clock prescaler: to get the best compromise between speed and current consumption the clock frequency to the CPU and peripherals can be adjusted by a programmable prescaler.
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STM8L051F3 Functional overview Figure 2. STM8L051F3 clock tree diagram SWIM[3:0] OSC_OUT OSC_IN HSE OSC 1-16 MHz HSE HSI HSI RC 1-16 MHz LSI SYSCLK prescaler /1;2;4;8;16;32;64 LSE SYSCLK to core and memory PCLK to peripherals Peripheral Clock enable (13 bits) LSE BEEPCLK to BEEP CLKBEEPSEL[1:0] LSI LSI RC 38 kHz IWDGCLK to IWDG RTCSEL[3:0] OSC32_OUT OSC32_IN CCO RTC prescaler /1;2;4;8;16;32;64 LSE OSC 32.
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Functional overview 3.5 STM8L051F3 Low power real-time clock The real-time clock (RTC) is an independent binary coded decimal (BCD) timer/counter. Six byte locations contain the second, minute, hour (12/24 hour), week day, date, month, year, in BCD (binary coded decimal) format. Correction for 28, 29 (leap year), 30, and 31 day months are made automatically. It provides a programmable alarm and programmable periodic interrupts with wakeup from Halt capability. 3.6 • Periodic wakeup time using the 32.
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STM8L051F3 3.9 Functional overview System configuration controller and routing interface The system configuration controller provides the capability to remap some alternate functions on different I/O ports. TIM4 and ADC1 DMA channels can also be remapped. The highly flexible routing interface controls the routing of internal analog signals to ADC1 and the internal reference voltage VREFINT. 3.
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Functional overview 3.11.1 STM8L051F3 Window watchdog timer The window watchdog (WWDG) is used to detect the occurrence of a software fault, usually generated by external interferences or by unexpected logical conditions, which cause the application program to abandon its normal sequence. 3.11.2 Independent watchdog timer The independent watchdog peripheral (IWDG) can be used to resolve processor malfunctions due to hardware or software failures.
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STM8L051F3 3.13.3 Functional overview USART The USART interface (USART1) allows full duplex, asynchronous communications with external devices requiring an industry standard NRZ asynchronous serial data format. It offers a very wide range of baud rates. • 1 Mbit/s full duplex SCI • SPI1 emulation • High precision baud rate generator • Smartcard emulation • IrDA SIR encoder decoder • Single wire half duplex mode Note: USART1 can be served by the DMA1 Controller. 3.
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Functional overview STM8L051F3 Bootloader STM8L051F3 features a built-in bootloader. See STM8 bootloader user manual (UM0560). The bootloader is used to download application software into the device memories, including RAM, program and data memory, using standard serial interfaces. It is a complementary solution to programming via the SWIM debugging interface. 22/96 Downloaded from Arrow.com.
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STM8L051F3 4 Pin description Pin description Figure 3. STM8L051F3 20-pin TSSOP20 package pinout PC5 PC6 PA0 NRST / PA1 PA2 PA3 VSS/VSSA/VREFVDD/VDDA/VREF+ PD0 PB0 PC4 PC1 1 20 2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 PC0 PB7 PB6 PB5 PB4 PB3 PB2 10 11 PB1 MS18280V1 Table 3.
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Pin description STM8L051F3 Table 4. STM8L051F3 pin description (2)/ Main function (after reset) - X - HS - X Reset PP Ext.
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STM8L051F3 Pin description Table 4.
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Memory and register map 5 STM8L051F3 Memory and register map The following sections describe the mapping of the device’s memory and peripherals. 5.1 Memory mapping The memory map is shown in Figure 4. Figure 4.
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STM8L051F3 Memory and register map address. 2. Refer to Table 7 for an overview of hardware register mapping, to Table 6 for details on I/O port hardware registers, and to Table 8 for information on CPU/SWIM/debug module controller registers. Table 5. Flash and RAM boundary addresses Memory area Size Start address End address RAM 1 Kbyte 0x00 0000 0x00 03FF Flash program memory 8 Kbytes 0x00 8000 0x00 9FFF 5.2 Register map Table 6.
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Memory and register map STM8L051F3 Table 7.
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STM8L051F3 Memory and register map Table 7.
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Memory and register map STM8L051F3 Table 7.
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STM8L051F3 Memory and register map Table 7.
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Memory and register map STM8L051F3 Table 7.
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STM8L051F3 Memory and register map Table 7.
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Memory and register map STM8L051F3 Table 7.
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STM8L051F3 Memory and register map Table 7.
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Memory and register map STM8L051F3 Table 7.
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STM8L051F3 Memory and register map Table 7.
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Memory and register map STM8L051F3 Table 8.
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STM8L051F3 Memory and register map Table 8. CPU/SWIM/debug module/interrupt controller registers (continued) Address Block 0x00 7F97 0x00 7F98 0x00 7F99 DM 0x00 7F9A 0x00 7F9B to 0x00 7F9F Register label Register name Reset status DM_CR2 DM Debug module control register 2 0x00 DM_CSR1 DM Debug module control/status register 1 0x10 DM_CSR2 DM Debug module control/status register 2 0x00 DM_ENFCTR DM enable function register 0xFF Reserved area (5 bytes) 1.
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Interrupt vector mapping 6 STM8L051F3 Interrupt vector mapping The interrupt vector mapping is described in Table 9. I IRQ No. Table 9.
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STM8L051F3 Interrupt vector mapping Table 9.
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Option bytes 7 STM8L051F3 Option bytes Option bytes contain configurations for device hardware features as well as the memory protection of the device. They are stored in a dedicated memory block. All option bytes can be modified in ICP mode (with SWIM) by accessing the EEPROM address. See Table 10 for details on option byte addresses.
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STM8L051F3 Option bytes Table 11. Option byte description Option byte No. Option description OPT0 ROP[7:0] Memory readout protection (ROP) 0xAA: Disable readout protection (write access via SWIM protocol) Refer to the “Readout protection” section in the STM8L050J3, STM8L051F3, STM8L052C6, STM8L052R8 MCUs and STM8L151/L152, STM8L162, STM8AL31, STM8AL3L lines reference manual (RM0031). OPT1 UBC[7:0] Size of the user boot code area 0x00: UBC is not protected. 0x01: Page 0 is write protected.
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Option bytes STM8L051F3 Table 11. Option byte description (continued) Option byte No. OPT5 Option description BOR_ON: 0: Brownout reset off 1: Brownout reset on BOR_TH[3:1]: Brownout reset thresholds. Refer to for details on the thresholds according to the value of BOR_TH bits. OPTBL 44/96 Downloaded from Arrow.com. OPTBL[15:0]: This option is checked by the boot ROM code after reset.
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STM8L051F3 8 Electrical parameters Electrical parameters This section describes the quantification of the given device’s parameters. 8.1 Parameter conditions Unless otherwise specified, all voltages are referred to VSS. 8.1.
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Electrical parameters 8.1.5 STM8L051F3 Pin input voltage The input voltage measurement on a pin of the device is described in Figure 6. Figure 6. Pin input voltage STM8 PIN VIN MSv37775V1 8.2 Absolute maximum ratings Stresses above the absolute maximum ratings listed in Table 12: Voltage characteristics, Table 13: Current characteristics, and Table 14: Thermal characteristics may cause permanent damage to the device.
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STM8L051F3 Electrical parameters Table 13. Current characteristics (continued) Symbol IIO Ratings Max. Output current sunk by IR_TIM pin (with high sink LED driver capability) 80 Output current sunk by any other I/O and control pin 25 Output current sourced by any I/Os and control pin IINJ(PIN) ΣIINJ(PIN) Unit - 25 Injected current on true open-drain pins (PC0 and PC1)(1) - 5 / +0 Injected current on five-volt tolerant (FT) pins (PA7 and PE0) (1) - 5 / +0 Injected current on 3.
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Electrical parameters 8.3 STM8L051F3 Operating conditions Subject to general operating conditions for VDD and TA. 8.3.1 General operating conditions The operating conditions define the conditions under which the device operates correctly according to its specification (see Table 15). Table 15. General operating conditions Symbol fSYSCLK(1) Parameter System clock frequency Conditions Min. Max. Unit 1.8 V ≤ VDD < 3.6 V 0 16 MHz - 1.8 3.6 V Must be at the same potential as VDD 1.8 3.
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STM8L051F3 8.3.2 Electrical parameters Embedded reset and power control block characteristics The reset and power block parameters are described in Table 16 and are derived from tests performed under the ambient temperature conditions summarized in Table 15: General operating conditions. Table 16.
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Electrical parameters STM8L051F3 Figure 7. POR/BOR thresholds VDD VDD 3.6 V Operatin g power supply V DD BOR threshold_0 1.8 V BOR threshold VBOR0 VPDR PDR threshold Reset Safe reset Safe reset release without BOR = battery life extension Internal NRST with BOR with without BOR BOR Time BOR always active at power up BOR activated by user for power-down detection ai17033b 8.3.
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STM8L051F3 Electrical parameters Table 17. Total current consumption in Run mode Symbol Para meter Conditions(1) Unit 55 °C 85 °C fCPU = 125 kHz 0.39 0.47 0.49 fCPU = 1 MHz 0.48 0.56 0.58 fCPU = 4 MHz 0.75 0.84 0.86 fCPU = 8 MHz 1.10 1.20 1.25 fCPU = 16 MHz 1.85 1.93 2.12(5) fCPU = 125 kHz 0.05 0.06 0.09 fCPU = 1 MHz 0.18 0.19 0.20 fCPU = 4 MHz 0.55 0.62 0.64 fCPU = 8 MHz 0.99 1.20 1.21 fCPU = 16 MHz 1.90 2.22 2.23(5) LSI RC osc. (typ. 38 kHz) fCPU = fLSI 0.
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Electrical parameters STM8L051F3 4. Oscillator bypassed (HSEBYP = 1 in CLK_ECKCR). When configured for external crystal, the HSE consumption (IDD HSE) must be added. Refer to Table 28. 5. Tested in production. 6. The run from Flash consumption can be approximated with the linear formula: IDD(run_from_Flash) = Freq * 195 µA/MHz + 440 µA 7. Oscillator bypassed (LSEBYP = 1 in CLK_ECKCR). When configured for extenal crystal, the LSE consumption (IDD LSE) must be added. Refer to Table 29. Figure 8. Typ.
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STM8L051F3 Electrical parameters In the following table, data is based on characterization results, unless otherwise specified. Table 18. Total current consumption in Wait mode Max Conditions(1) Symbol Parameter HSI CPU not clocked, all peripherals OFF, Supply code executed IDD(Wait) current in from RAM Wait mode with Flash in IDDQ mode(2), VDD from 1.8 V to 3.6 V Typ fCPU = 125 kHz 0.33 0.39 0.41 fCPU = 1 MHz 0.35 0.41 0.44 fCPU = 4 MHz 0.42 0.51 0.52 fCPU = 8 MHz 0.52 0.57 0.
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Electrical parameters STM8L051F3 4. Oscillator bypassed (LSEBYP = 1 in CLK_ECKCR). When configured for extenal crystal, the LSE consumption (IDD HSE) must be added. Refer to Table 29. Figure 9. Typ. IDD(Wait) vs. VDD, fCPU = 16 MHz 1) 1000 950 IDD(WAIT)HSI [μA] 900 850 800 750 700 -40°C 650 25°C 600 85°C 550 500 1.8 2.1 2.6 3.1 VDD [V] 1. Typical current consumption measured with code executed from Flash memory. 54/96 Downloaded from Arrow.com. DS9178 Rev 4 3.
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STM8L051F3 Electrical parameters In the following table, data is based on characterization results, unless otherwise specified. Table 19. Total current consumption and timing in Low power run mode at VDD = 1.8 V to 3.6 V Symbol Conditions(1) Parameter all peripherals OFF LSI RC osc. (at 38 kHz) with TIM2 active(2) IDD(LPR) Supply current in Low power run mode all peripherals OFF (3) LSE external clock (32.768 kHz) with TIM2 active (2) Typ Max Unit TA = -40 °C to 25 °C 5.1 5.4 TA = 55 °C 5.
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Electrical parameters STM8L051F3 In the following table, data is based on characterization results, unless otherwise specified. Table 20. Total current consumption in Low power wait mode at VDD = 1.8 V to 3.6 V Symbol Conditions(1) Parameter Typ Max Unit TA = -40 °C to 25 °C all peripherals OFF LSI RC osc. (at 38 kHz) with TIM2 IDD(LPW) active(2) Supply current in Low power wait mode all peripherals OFF LSE external clock(3) (32.768 kHz) with TIM2 active (2) 3 3.3 TA = 55 °C 3.3 3.
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STM8L051F3 Electrical parameters In the following table, data is based on characterization results, unless otherwise specified. Table 21. Total current consumption and timing in Active-halt mode at VDD = 1.8 V to 3.6 V Symbol Conditions (1) Parameter LSI RC (at 38 kHz) IDD(AH) Supply current in Active-halt mode LSE external clock (32.768 kHz)(2) IDD(WUFAH) Supply current during wakeup time from Active-halt mode (using HSI) Typ Max TA = -40 °C to 25 °C 0.9 2.1 TA = 55 °C 1.2 3 TA = 85 °C 1.
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Electrical parameters STM8L051F3 In the following table, data is based on characterization results, unless otherwise specified. Table 23. Total current consumption and timing in Halt mode at VDD = 1.8 to 3.
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STM8L051F3 Electrical parameters Current consumption of on-chip peripherals Table 24. Peripheral current consumption Symbol Typ. VDD = 3.
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Electrical parameters STM8L051F3 Table 25. Current consumption under external reset Symbol IDD(RST) Parameter Conditions Supply current under external reset (1) All pins are externally tied to VDD Typ VDD = 1.8 V 48 VDD = 3 V 76 VDD = 3.6 V 91 Unit µA 1. All pins except PA0, PB0 and PB4 are floating under reset. PA0, PB0 and PB4 are configured with pull-up under reset. 8.3.
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STM8L051F3 Electrical parameters HSE crystal/ceramic resonator oscillator The HSE clock can be supplied with a 1 to 16 MHz crystal/ceramic resonator oscillator. All the information given in this paragraph is based on characterization results with specified typical external components. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time.
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Electrical parameters STM8L051F3 LSE crystal/ceramic resonator oscillator The LSE clock can be supplied with a 32.768 kHz crystal/ceramic resonator oscillator. All the information given in this paragraph is based on characterization results with specified typical external components. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time.
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STM8L051F3 Electrical parameters Internal clock sources Subject to general operating conditions for VDD, and TA. High speed internal RC oscillator (HSI) In the following table, data is based on characterization results, not tested in production, unless otherwise specified. Table 30. HSI oscillator characteristics Symbol fHSI ACCHSI Conditions(1) Parameter Frequency Min Typ - 16 VDD = 3.0 V Accuracy of HSI oscillator (factory calibrated) -1 -2.
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Electrical parameters STM8L051F3 Low speed internal RC oscillator (LSI) In the following table, data is based on characterization results, not tested in production. Table 31. LSI oscillator characteristics Parameter (1) Symbol fLSI Conditions(1) Min Typ Max Unit - 26 38 56 kHz Frequency tsu(LSI) LSI oscillator wakeup time IDD(LSI) LSI oscillator frequency drift(3) 0 °C ≤TA ≤ 85 °C (2) - - 200 -12 - 11 µs % 1. VDD = 1.8 V to 3.6 V, TA = -40 to 85 °C unless otherwise specified. 2.
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STM8L051F3 8.3.5 Electrical parameters Memory characteristics TA = -40 to 85 °C unless otherwise specified. Table 32. RAM and hardware registers Symbol Parameter Conditions Min Typ Max Unit VRM Data retention mode (1) Halt mode (or Reset) 1.8 - - V 1. Minimum supply voltage without losing data stored in RAM (in Halt mode or under Reset) or in hardware registers (only in Halt mode). Guaranteed by characterization. Flash memory Table 33.
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Electrical parameters 8.3.6 STM8L051F3 I/O current injection characteristics As a general rule, current injection to the I/O pins, due to external voltage below VSS or above VDD (for standard pins) should be avoided during normal product operation. However, in order to give an indication of the robustness of the microcontroller in cases when abnormal injection accidentally happens, susceptibility tests are performed on a sample basis during device characterization.
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STM8L051F3 Electrical parameters Table 35. I/O static characteristics Symbol VIL Conditions(1) Min Input voltage on true open-drain pins (PC0 and PC1) VSS-0.3 0.3 x VDD Input voltage on five-volt tolerant (FT) pins (PA7 and PE0) VSS-0.3 0.3 x VDD Input voltage on 3.6 V tolerant (TT) pins VSS-0.3 0.3 x VDD Input voltage on any other pin VSS-0.3 0.
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Electrical parameters STM8L051F3 Figure 16. Typical VIL and VIH vs VDD (high sink I/Os) 3 -40°C 25°C 2.5 85°C VIL and VIH [V] 2 1.5 1 0.5 0 1.8 2.1 2.6 3.1 3.6 VDD [V] ai18220c Figure 17. Typical VIL and VIH vs VDD (true open drain I/Os) 3 -40°C 25°C 2.5 VIL and VIH [V] 85°C 2 1.5 1 0.5 0 1.8 2.1 2.6 VDD [V] 3.1 3.6 ai18221b 68/96 Downloaded from Arrow.com.
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STM8L051F3 Electrical parameters Figure 18. Typical pull-up resistance RPU vs VDD with VIN=VSS 60 -40°C 55 25°C Pull-up resistance [kΩ] 85°C 50 45 40 35 30 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 VDD [V] ai18222b Figure 19. Typical pull-up current Ipu vs VDD with VIN=VSS 120 -40°C 25°C 100 Pull-up current [μA] 85°C 80 60 40 20 0 1.8 1.95 2.1 2.25 2.4 2.55 2.7 2.85 3 3.15 3.3 3.45 3.6 VDD [V] ai18223b DS9178 Rev 4 69/96 87 Downloaded from Arrow.com.
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Electrical parameters STM8L051F3 Output driving current Subject to general operating conditions for VDD and TA unless otherwise specified. Table 36. Output driving current (high sink ports) I/O Symbol Type Output low level voltage for an I/O pin High sink VOL (1) Parameter VOH (2) Output high level voltage for an I/O pin Conditions Min Max Unit IIO = +2 mA, VDD = 3.0 V - 0.45 V IIO = +2 mA, VDD = 1.8 V - 0.45 V IIO = +10 mA, VDD = 3.0 V - 0.7 V IIO = -2 mA, VDD = 3.0 V VDD-0.
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STM8L051F3 Electrical parameters Figure 20. Typ. VOL @ VDD = 3.0 V (high sink ports) Figure 21. Typ. VOL @ VDD = 1.8 V (high sink ports) 1 0.7 -40°C 25°C 85°C 0.6 -40°C 25°C 85°C 0.5 VOL [V] VOL [V] 0.75 0.5 0.25 0.4 0.3 0.2 0.1 0 0 2 4 6 8 10 12 14 16 18 0 20 0 IOL [mA] 1 2 3 4 ai18226V2 Figure 22. Typ. VOL @ VDD = 3.0 V (true open drain ports) 5 6 7 IOL [mA] Figure 23. Typ. VOL @ VDD = 1.8 V (true open drain ports) 0.5 0.5 -40°C 25°C 85°C 0.4 0.
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Electrical parameters STM8L051F3 NRST pin Subject to general operating conditions for VDD and TA unless otherwise specified. Table 39. NRST pin characteristics Symbol Parameter Conditions Min Typ Max VIL(NRST) NRST input low level voltage (1) - VSS - 0.8 VIH(NRST) NRST input high level voltage (1) - 1.4 - VDD IOL = 2 mA for 2.7 V ≤VDD ≤ 3.6 V - - IOL = 1.5 mA for VDD < 2.7 V - VOL(NRST) VHYST RPU(NRST) NRST output low level voltage (1) NRST input hysteresis(3) (1) V 0.
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STM8L051F3 Electrical parameters Figure 27. Typical NRST pull-up current Ipu vs VDD 120 -40°C 100 25°C Pull-up current [μA] 85°C 80 60 40 20 0 1.8 1.95 2.1 2.25 2.4 2.55 2.7 2.85 3 3.15 3.3 3.45 3.6 VDD [V] ai18225b The reset network shown in Figure 28 protects the device against parasitic resets. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max. level specified in Table 39. Otherwise the reset is not taken into account internally.
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Electrical parameters 8.3.8 STM8L051F3 Communication interfaces SPI1 - Serial peripheral interface Unless otherwise specified, the parameters given in Table 40 are derived from tests performed under ambient temperature, fSYSCLK frequency and VDD supply voltage conditions summarized in Section 8.3.1. Refer to I/O port characteristics for more details on the input/output alternate function characteristics (NSS, SCK, MOSI, MISO). Table 40.
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STM8L051F3 Electrical parameters Figure 29. SPI1 timing diagram - slave mode and CPHA=0 Figure 30. SPI1 timing diagram - slave mode and CPHA=1(1) NSS input SCK input tSU(NSS) CPHA=1 CPOL=0 CPHA=1 CPOL=1 tw(SCKH) tw(SCKL) th(SO) tv(SO) ta(SO) MISO OUTPUT MSB OUT BIT6 OUT tr(SCK) tf(SCK) tdis(SO) LSB OUT th(SI) tsu(SI) MOSI INPUT th(NSS) tc(SCK) MSB IN BIT 1 IN LSB IN ai14135b 1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD. DS9178 Rev 4 75/96 87 Downloaded from Arrow.
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Electrical parameters STM8L051F3 Figure 31. SPI1 timing diagram - master mode(1) 1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD. 76/96 Downloaded from Arrow.com.
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STM8L051F3 Electrical parameters I2C - Inter IC control interface Subject to general operating conditions for VDD, fSYSCLK, and TA unless otherwise specified. The STM8L I2C interface (I2C1) meets the requirements of the Standard I2C communication protocol described in the following table with the restriction mentioned below: Refer to I/O port characteristics for more details on the input/output alternate function characteristics (SDA and SCL). Table 41.
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Electrical parameters STM8L051F3 Figure 32. Typical application with I2C bus and timing diagram 1) 1. Measurement points are done at CMOS levels: 0.3 x VDD and 0.7 x VDD 78/96 Downloaded from Arrow.com.
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STM8L051F3 8.3.9 Electrical parameters Embedded reference voltage In the following table, data is based on characterization results, not tested in production, unless otherwise specified. Table 42. Reference voltage characteristics Symbol Parameter Conditions Min Typ Max. Unit Internal reference voltage consumption - - 1.4 - µA ADC sampling time when reading the internal reference voltage - - 5 10 µs Internal reference voltage buffer consumption (used for ADC) - - 13.
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Electrical parameters STM8L051F3 Table 43. ADC1 characteristics Symbol Parameter VDDA Analog supply voltage VREF+ Reference supply voltage VREFIVDDA IVREF+ Conditions Min Typ Max Unit - 1.8 - 3.6 V 2.4 V ≤VDDA≤ 3.6 V 2.4 - VDDA V 1.8 V ≤VDDA≤ 2.
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STM8L051F3 Electrical parameters 1. The current consumption through VREF is composed of two parameters: - one constant (max 300 µA) - one variable (max 400 µA), only during sampling time + 2 first conversion pulses. So, peak consumption is 300+400 = 700 µA and average consumption is 300 + [(4 sampling + 2) /16] x 400 = 450 µA at 1Msps 2. VREF- or VDDA must be tied to ground. 3. Guaranteed by design. 4. Minimum sampling and conversion time is reached for maximum Rext = 0.5 kΩ. 5.
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Electrical parameters STM8L051F3 In the following three tables, data is guaranteed by characterization result, not tested in production. Table 44. ADC1 accuracy with VDDA = 3.3 V to 2.5 V Symbol Parameter Conditions Typ Max 1 1.6 Differential non linearity fADC = 8 MHz 1 1.6 fADC = 4 MHz 1 1.5 fADC = 16 MHz 1.2 2 fADC = 8 MHz 1.2 1.8 fADC = 4 MHz 1.2 1.7 fADC = 16 MHz 2.2 3.0 fADC = 8 MHz 1.8 2.5 fADC = 4 MHz 1.8 2.3 fADC = 16 MHz 1.5 2 fADC = 8 MHz 1 1.
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STM8L051F3 Electrical parameters Figure 33. ADC1 accuracy characteristics Figure 34. Typical connection diagram using the ADC STM8 VDD Sample and hold ADC converter VT 0.6V (1) RAIN Cparasitic (2) VAIN RADC AINx VT 0.6V 12-bit converter CADC(1) I L± 50nA ai17090f 1. Refer to Table 47 for the values of RAIN and CADC. 2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the pad capacitance (roughly 7 pF).
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Electrical parameters STM8L051F3 Table 47. RAIN max for fADC = 16 MHz(1) RAIN max (kohm) Ts (cycles) Ts (µs) Slow channels 2.4 V < VDDA < 3.6 V 1.8 V < VDDA < 2.4 V 4 0.25 Not allowed Not allowed 9 0.5625 0.8 Not allowed 16 1 2.0 0.8 24 1.5 3.0 1.8 48 3 6.8 4.0 96 6 15.0 10.0 192 12 32.0 25.0 384 24 50.0 50.0 1. Guaranteed by design.
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STM8L051F3 Electrical parameters Figure 37. Power supply and reference decoupling (VREF+ connected to VDDA) STM8L VREF+/VDDA Supply 1 μF // 10 nF VREF-/VSSA ai17032d 8.3.11 EMC characteristics Susceptibility tests are performed on a sample basis during product characterization.
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Electrical parameters STM8L051F3 Most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1 second. To complete these trials, ESD stress can be applied directly on the device, over the range of specification values. When unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note AN1015). Table 48.
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STM8L051F3 Electrical parameters Table 50. ESD absolute maximum ratings Symbol VESD(HBM) VESD(CDM) Ratings Conditions Electrostatic discharge voltage (human body model) Electrostatic discharge voltage (charge device model) Maximum value (1) Unit 2000 TA = +25 °C V 500 1. Guaranteed by characterization results. Static latch-up • LU: 3 complementary static tests are required on 6 parts to assess the latch-up performance.
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Package characteristics STM8L051F3 9 Package characteristics 9.1 ECOPACK® In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. 88/96 Downloaded from Arrow.com.
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STM8L051F3 Package characteristics 9.2 Package mechanical data 9.3 TSSOP20 package information Figure 38. TSSOP20 – 20-lead thin shrink small outline, 6.5 x 4.4 mm, 0.65 mm pitch, package outline D 20 11 c E1 E 1 SEATING PLANE C 0.25 mm GAUGE PLANE 10 PIN 1 IDENTIFICATION k aaa C A1 A A2 b L L1 e YA_ME_V3 1. Drawing is not to scale. Table 52. TSSOP20 – 20-lead thin shrink small outline, 6.5 x 4.4 mm, 0.65 mm pitch, package mechanical data inches(1) millimeters Symbol Min. Typ. Max.
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Package characteristics STM8L051F3 1. Values in inches are converted from mm and rounded to four decimal digits. 2. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusions or gate burrs shall not exceed 0.15mm per side. 3. Dimension “E1” does not include interlead flash or protrusions. Interlead flash or protrusions shall not exceed 0.25mm per side. Figure 39. TSSOP20 – 20-lead thin shrink small outline, 6.5 x 4.4 mm, 0.65 mm pitch, package footprint 0.25 6.
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STM8L051F3 Package characteristics Device marking for TSSOP20 – 20-lead thin shrink small outline, 6.5 x 4.4 mm, 0.65 mm pitch The following figure gives an example of topside marking orientation versus pin 1/ball A1 identifier location. Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below. Figure 40. Device marking for TSSOP20 – 20-lead thin shrink small outline, 6.5 x 4.4 mm, 0.
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Package characteristics 9.4 STM8L051F3 Thermal characteristics The maximum chip junction temperature (TJmax) must never exceed the values given in Table 15: General operating conditions on page 48.
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STM8L051F3 10 Ordering information Ordering information Figure 41.
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Revision history 11 STM8L051F3 Revision history Table 54. Document revision history Date Revision 01-Aug-2012 1 Initial release.
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STM8L051F3 Revision history Table 54. Document revision history Date 04-Jul-2017 Revision 3 (Cont.) Changes Updated (continuation): – Figure 37: Power supply and reference decoupling (VREF+ connected to VDDA) – Figure 38: TSSOP20 – 20-lead thin shrink small outline, 6.5 x 4.4 mm, 0.65 mm pitch, package outline – Figure 39: TSSOP20 – 20-lead thin shrink small outline, 6.5 x 4.4 mm, 0.
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STM8L051F3 IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement.