Datasheet

ManualsBrandsST ManualsEmbedded Processors & ControllersMicrocontroller 8bit 8KB TSSOP

DS9178 Rev 4 27/96

STM8L051F3 Memory and register map

address.

2. Refer to Table 7 for an overview of hardware register mapping, to Table 6 for details on I/O port hardware

registers, and to Table 8 for information on CPU/SWIM/debug module controller registers.

5.2 Register map

Table 5. Flash and RAM boundary addresses

Memory area Size Start address End address

RAM 1 Kbyte 0x00 0000 0x00 03FF

Flash program memory 8 Kbytes 0x00 8000 0x00 9FFF

Table 6. I/O port hardware register map

Address Block Register label Register name

Reset

status

0x00 5000

Port A

PA_ODR Port A data output latch register 0x00

0x00 5001 PA_IDR Port A input pin value register 0xXX

0x00 5002 PA_DDR Port A data direction register 0x00

0x00 5003 PA_CR1 Port A control register 1 0x01

0x00 5004 PA_CR2 Port A control register 2 0x00

0x00 5005

Port B

PB_ODR Port B data output latch register 0x00

0x00 5006 PB_IDR Port B input pin value register 0xXX

0x00 5007 PB_DDR Port B data direction register 0x00

0x00 5008 PB_CR1 Port B control register 1 0x00

0x00 5009 PB_CR2 Port B control register 2 0x00

0x00 500A

Port C

PC_ODR Port C data output latch register 0x00

0x00 500B PB_IDR Port C input pin value register 0xXX

0x00 500C PC_DDR Port C data direction register 0x00

0x00 500D PC_CR1 Port C control register 1 0x00

0x00 500E PC_CR2 Port C control register 2 0x00

0x00 500F

Port D

PD_ODR Port D data output latch register 0x00

0x00 5010 PD_IDR Port D input pin value register 0xXX

0x00 5011 PD_DDR Port D data direction register 0x00

0x00 5012 PD_CR1 Port D control register 1 0x00

0x00 5013 PD_CR2 Port D control register 2 0x00

0x00 5014

0x00 501D

Reserved area (0 bytes)

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