Datasheet

DS9178 Rev 4 95/96
STM8L051F3 Revision history
95
04-Jul-2017
3
(Cont.)
Updated (continuation):
– Figure 37: Power supply and reference decoupling (VREF+
connected to VDDA)
– Figure 38: TSSOP20 – 20-lead thin shrink small outline, 6.5 x
4.4 mm, 0.65 mm pitch, package outline
– Figure 39: TSSOP20 – 20-lead thin shrink small outline, 6.5 x
4.4 mm, 0.65 mm pitch, package footprint
– Table 25: Current consumption under external reset
Added
– Section : Device marking for TSSOP20 – 20-lead thin shrink small
outline, 6.5 x 4.4 mm, 0.65 mm pitch
– Figure 40: Device marking for TSSOP20 – 20-lead thin shrink small
outline, 6.5 x 4.4 mm, 0.65 mm pitch example
07-Sep-2018 4
Updated:
– 12-bit ADC up to 1 Msps/10 channels feature on cover page
– Section 3.8: Analog-to-digital converter
– Table 4: STM8L051F3 pin description
– Table 7: General hardware register map
– Table 43: ADC1 characteristics
– Table 47: R
AIN
max for f
ADC
= 16 MHz
– Added introduction to following sections:
Section 3.2: Central processing unit STM8
Section 3.3: Reset and supply management
Section 3.13: Communication interfaces
Section 3.15: Development support
Section 5: Memory and register map
Section 6: Interrupt vector mapping
Section 8: Electrical parameters
Section 8.3.1: General operating conditions
Section 8.3.2: Embedded reset and power control block
characteristics
Table 54. Document revision history
Date Revision Changes
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