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This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to

change without notice.

June 2017 DocID030584 Rev 2 1/84

STM8S001J3

16 MHz STM8S 8-bit MCU, 8-Kbyte Flash memory, 128-byte data

EEPROM, 10-bit ADC, 3 timers, UART, SPI, I2C

Datasheet - preliminary data

Features

Core

• 16 MHz advanced STM8 core with Harvard

architecture and 3-stage pipeline

• Extended instruction set

Memories

• Program memory: 8 Kbytes Flash memory;

data retention 20 years at 55 °C after 100

cycles

• RAM: 1 Kbyte

• Data memory: 128-byte true data EEPROM;

endurance up to 100 k write/erase cycles

Clock, reset and supply management

• 2.95 V to 5.5 V operating voltage

• Flexible clock control, 3 master clock sources

– External clock input

– Internal, user-trimmable 16 MHz RC

– Internal low-power 128 kHz RC

• Clock security system with clock monitor

• Power management

– Low-power modes (wait, active-halt, halt)

– Switch-off peripheral clocks individually

– Permanently active, low-consumption

power-on and power-down reset

Interrupt management

• Nested interrupt controller with 32 interrupts

• Up to 5 external interrupts

Timers

• Advanced control timer: 16-bit, 2 CAPCOM

channels, 2 outputs, dead-time insertion and

flexible synchronization

• 16-bit general purpose timer, with 3 CAPCOM

channels (IC, OC or PWM)

• 8-bit basic timer with 8-bit prescaler

• Auto wakeup timer

• Window and independent watchdog timers

Communications interfaces

• UART, SmartCard, IrDA, LIN master mode

• SPI unidirectional interface up to 8 Mbit/s

(master simplex mode, slave receiver only)

• I2C interface up to 400 Kbit/s

Analog to digital converter (ADC)

• 10-bit ADC, ± 1 LSB ADC with up to 3

multiplexed channels, scan mode and analog

watchdog

I/Os

• Up to 5 I/Os including 4 high-sink outputs

• Highly robust I/O design, immune against

current injection

Development support

• Embedded single-wire interface module

(SWIM) or fast on-chip programming and non-

intrusive debugging

SO8N

4.9x6 mm or 150 mils width

www.st.com

Downloaded from Arrow.com.

Summary of content (84 pages)

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STM8S001J3 16 MHz STM8S 8-bit MCU, 8-Kbyte Flash memory, 128-byte data EEPROM, 10-bit ADC, 3 timers, UART, SPI, I2C Datasheet - preliminary data Features Core • 16 MHz advanced STM8 core with Harvard architecture and 3-stage pipeline SO8N 4.
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Contents STM8S001J3 Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4 Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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STM8S001J3 Contents 6.2.3 CPU/SWIM/debug module/interrupt controller registers . . . . . . . . . . . . 33 7 Interrupt vector mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 8 Option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 8.1 9 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 9.1 10 Alternate function remapping bits . . . . . . . . . . . . . . . . . .
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Contents STM8S001J3 12.2 12.3 13 4/84 Downloaded from Arrow.com. Software tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 12.2.1 STM8 toolset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 12.2.2 C and assembly toolchains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Programming tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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STM8S001J3 List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. Table 45. Table 46. Table 47.
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List of tables Table 49. Table 50. 6/84 Downloaded from Arrow.com. STM8S001J3 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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STM8S001J3 List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40. STM8S001J3 block diagram . . . . .
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Introduction 1 STM8S001J3 Introduction This datasheet contains the description of the STM8S001J3 features, pinout, electrical characteristics, mechanical data and ordering information. 8/84 Downloaded from Arrow.com. • For complete information on the STM8S microcontroller memory, registers and peripherals, please refer to the STM8S and STM8A microcontroller families reference manual (RM0016).
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STM8S001J3 2 Description Description The STM8S001J3 8-bit microcontrollers offer 8 Kbytes of Flash program memory, plus integrated true data EEPROM. It is referred to as low-density device in the STM8S microcontroller family reference manual (RM0016). The STM8S001J3 device provides the following benefits: performance, robustness and reduced system cost.
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Block diagram 3 STM8S001J3 Block diagram Figure 1. STM8S001J3 block diagram 5HVHW EORFN ([W &ORFN LQSXW ± 0+] &ORFN FRQWUROOHU 5HVHW 5& LQW 0+] 'HWHFWRU 325 %25 5& LQW N+] &ORFN WR SHULSKHUDOV DQG FRUH :LQGRZ :'* 670 FRUH ,QGHSHQGHQW :'* 6LQJOH ZLUH GHEXJ LQWHUIDFH 'HEXJ 6:,0 .E\WH SURJUDP )ODVK .ELW V 0ELW V , & 8QLGLUHFWLRQDO 63, /,1 PDVWHU 8$57 8S WR FKDQQHOV $'& $GGUHVV DQG GDWD EXV E\WH GDWD ((3520 .E\WH 5$0 ELW DGYDQFHG FRQWURO WLP
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STM8S001J3 4 Functional overview Functional overview The following section intends to give an overview of the basic features of the STM8S001J3 functional modules and peripherals. For more detailed information please refer to the corresponding family reference manual (RM0016). 4.1 Central processing unit STM8 The 8-bit STM8 core is designed for code efficiency and performance.
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Functional overview 4.2 STM8S001J3 Single wire interface module (SWIM) and debug module (DM) The single wire interface module and debug module permits non-intrusive, real-time incircuit debugging and fast memory programming. SWIM Single wire interface module for direct access to the debug module and memory programming. The interface can be activated in all device operation modes. The maximum data transmission speed is 145 byte/ms.
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STM8S001J3 Functional overview There are two levels of write protection. The first level is known as MASS (memory access security system). MASS is always enabled and protects the main Flash program memory, data EEPROM and option bytes. To perform in-application programming (IAP), this write protection can be removed by writing a MASS key sequence in a control register. This allows the application to modify the content of main program memory and data EEPROM, or to reprogram the device option bytes.
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Functional overview STM8S001J3 Recommendation for the device's programming: The device's 8 Kbytes program memory is not empty on virgin devices; there is code loop implemented on the reset vector. It is recommended to keep valid code loop in the device to avoid the program execution from an invalid memory address (which would be any memory address out of 8 Kbytes program memory space).
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STM8S001J3 4.5 Functional overview Clock controller The clock controller distributes the system clock (fMASTER) coming from different oscillators to the core and the peripherals. It also manages clock gating for low power modes and ensures clock robustness. Features • Clock prescaler: To get the best compromise between speed and current consumption the clock frequency to the CPU and peripherals can be adjusted by a programmable prescaler.
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Functional overview 4.6 STM8S001J3 Power management For efficient power management, the application can be put in one of four different lowpower modes. You can configure each mode to obtain the best compromise between the lowest power consumption, the fastest start-up time and available wakeup sources. 4.7 • Wait mode: In this mode, the CPU is stopped, but peripherals are kept running. The wakeup is performed by an internal or external interrupt or reset.
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STM8S001J3 Functional overview Independent watchdog timer The independent watchdog peripheral can be used to resolve processor malfunctions due to hardware or software failures. It is clocked by the 128 kHz LSI internal RC clock source, and thus stays active even in case of a CPU clock failure The IWDG time base spans from 60 µs to 1 s. 4.8 4.
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Functional overview STM8S001J3 Table 3. TIM timer features Timer Counter size (bits) TIM1 16 Any integer from 1 to 65536 TIM2 16 TIM4 8 Counting CAPCOM Complem. Ext. mode trigger channels outputs Prescaler Up/down 2 1(1) No Any power of 2 from 1 to 32768 Up 3 0 No Any power of 2 from 1 to 128 Up 0 0 No Timer synchronization/ chaining No 1. TIM1_CH2N with TIM1_CH1 4.
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STM8S001J3 Functional overview Asynchronous communication (UART mode) • Full duplex communication - NRZ standard format (mark/space) • Programmable transmit and receive baud rates up to 1 Mbit/s (fCPU/16) and capable of following any standard baud rate regardless of the input frequency • Separate enable bits for transmitter and receiver • Two receiver wakeup modes: – Address bit (MSB) – Idle line (interrupt) • Transmission error detection with interrupt generation • Parity control LIN maste
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Pinouts and pin descriptions 5 STM8S001J3 Pinouts and pin descriptions This section presents the pinouts and pin descriptions for STM8S001J3. Table 4 introduces the legends and abbreviations that are used in the upcoming subsections. Table 4. Legend/abbreviations for STM8S001J3 pin description tables Type I = input, O = output, S = power supply Level Port and control configuration 5.
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STM8S001J3 Pinouts and pin descriptions Table 5. STM8S001J3 pin description PD6/ AIN6/ UART1 _RX I/O I/O Alternate function after remap [option bit] High sink(1) OD X X X HS O3 X X Port D6 Analog input 6/ UART1 data receive - X X X - O1 X X Port A1 External clock input (HSE clock) - 1 PA1/ OSCIN(2) Default alternate function Speed Type Main function (after PP reset) Ext. interr. Pin name SO8N Output wpu Input floating Pin no.
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Pinouts and pin descriptions STM8S001J3 Table 5. STM8S001J3 pin description (continued) PC6/ SPI_MOSI [TIM1_ CH1] PD1/ SWIM(4) 8 I/O I/O Default alternate function Alternate function after remap [option bit] High sink(1) Speed Type Main function (after PP reset) Ext. interr. Pin name SO8N Output wpu Input floating Pin no.
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STM8S001J3 5.2 Pinouts and pin descriptions Alternate function remapping As shown in the rightmost column of the pin description table, some alternate functions can be remapped at different I/O ports by programming one of eight AFR (alternate function remap) option bits. Refer to Section 8: Option bytes. When the remapping option is active, the default alternate function is no longer available. To use an alternate function, the corresponding peripheral must be enabled in the peripheral registers.
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Memory and register map STM8S001J3 6 Memory and register map 6.1 Memory map Figure 4. Memory map [ 5$0 .E\WH [ )) [ E\WH VWDFN 5HVHUYHG [ [ ) [ )) [ [ $ [ % 'DWD ((3520 5HVHUYHG 2SWLRQ E\WHV 5HVHUYHG [ ))) [ *3,2 DQG SHULSK UHJ [ )) [ 5HVHUYHG [ ()) [ ) [ ))) [ [ ) [ [ ))) [ $ &38 6:,0 GHEXJ ,7& UHJLVWHUV LQWHUUXSW YHFWRUV )ODVK SURJUDP PHPRU\ .E\WH
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STM8S001J3 Memory and register map Table 6 lists the boundary addresses for each memory size. The top of the stack is at the RAM end address in each case. Table 6. Flash, Data EEPROM and RAM boundary addresses Memory area Size (byte) Start address End address Flash program memory 8K 0x00 8000 0x00 9FFF RAM 1K 0x00 0000 0x00 03FF Data EEPROM 128 0x00 4000 0x00 407F 6.2 Register map 6.2.1 I/O port hardware register map Table 7.
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Memory and register map STM8S001J3 Table 7.
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STM8S001J3 Memory and register map Table 8.
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Memory and register map STM8S001J3 Table 8.
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STM8S001J3 Memory and register map Table 8.
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Memory and register map STM8S001J3 Table 8.
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STM8S001J3 Memory and register map Table 8.
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Memory and register map STM8S001J3 Table 8.
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STM8S001J3 6.2.3 Memory and register map CPU/SWIM/debug module/interrupt controller registers Table 9.
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Memory and register map STM8S001J3 Table 9.
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STM8S001J3 7 Interrupt vector mapping Interrupt vector mapping Table 10. Interrupt mapping IRQ no.
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Option bytes 8 STM8S001J3 Option bytes Option bytes contain configurations for device hardware features as well as the memory protection of the device. They are stored in a dedicated block of the memory. Except for the ROP (read-out protection) byte, each option byte has to be stored twice, in a regular form (OPTx) and a complemented one (NOPTx) for redundancy. Option bytes can be modified in ICP mode (via SWIM) by accessing the EEPROM address shown in Table 11: Option bytes below.
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STM8S001J3 Option bytes Table 12. Option byte description (continued) Option byte no. Description OPT1 UBC[7:0] User boot code area 0x00: no UBC, no write-protection 0x01: Pages 0 defined as UBC, memory write-protected 0x02: Pages 0 to 1 defined as UBC, memory write-protected Page 0 and page 1 contain the interrupt vectors. ... 0x7F: Pages 0 to 126 defined as UBC, memory write-protected Other values: Pages 0 to 127 defined as UBC, memory-write protected.
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Option bytes 8.1 STM8S001J3 Alternate function remapping bits Table 13. STM8S001J3 alternate function remapping bits for 8-pin devices Option byte number OPT2 Description AFR7Alternate function remapping option 7 0: AFR7 remapping option inactive: default alternate function(1) 1: Port C3 alternate function = TIM1_CH1N; port C4 alternate function = TIM1_CH2N. AFR6 Alternate function remapping option 6 Reserved. AFR5 Alternate function remapping option 5 Reserved.
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STM8S001J3 Electrical characteristics 9 Electrical characteristics 9.1 Parameter conditions Unless otherwise specified, all voltages are referred to VSS. 9.1.1 Minimum and maximum values Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at TA = 25 °C and TA = TAmax (given by the selected temperature range).
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Electrical characteristics STM8S001J3 Figure 6. Pin input voltage STM8 pin VIN 9.2 Absolute maximum ratings Stresses above the absolute maximum ratings listed in Table 14: Voltage characteristics, Table 15: Current characteristics, and Table 16: Thermal characteristics may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.
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STM8S001J3 Electrical characteristics Table 15. Current characteristics Symbol Max.
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Electrical characteristics 9.3 STM8S001J3 Operating conditions The device must be used in operating conditions that respect the parameters in Table 17. In addition, full account must be taken of all physical capacitor characteristics and tolerances. Table 17. General operating conditions Symbol Parameter Conditions Min Max Unit fCPU Internal CPU clock frequency - 0 16 MHz VDD Standard operating voltage - 2.95 5.5 V CEXT: capacitance of external capacitor - 470 3300 nF - 0.
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STM8S001J3 Electrical characteristics Table 18. Operating conditions at power-up/power-down Symbol tVDD tTEMP Parameter VDD rise time rate VDD fall time rate Reset release delay (1) Conditions Min Typ Max Unit - 2 - ∞ - 2 - ∞ VDD rising - - 1.7 ms µs/V VIT+ Power-on reset threshold - 2.6 2.7 2.85 V VIT- Brown-out reset threshold - 2.5 2.65 2.8 V VHYS(BOR) Brown-out reset hysteresis - - 70 - mV 1. Reset is always generated after a tTEMP delay.
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Electrical characteristics 9.3.1 STM8S001J3 VCAP external capacitor Stabilization for the main regulator is achieved connecting an external capacitor CEXT to the VCAP pin. CEXT is specified in Table 17. Care should be taken to limit the series inductance to less than 15 nH. Figure 8. External capacitor CEXT (6/ & (65 5/HDN 06Y 9 1. Legend: ESR is the equivalent series resistance and ESL is the equivalent inductance. 9.3.
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STM8S001J3 Electrical characteristics 2. Default clock configuration measured with all peripherals off. Table 20. Total current consumption with code execution in run mode at VDD = 3.3 V Symbol Typ Max(1) 2 2.3 HSI RC osc. (16 MHz) 1.5 2 HSE user ext. clock (16 MHz) 0.81 - HSI RC osc. (16 MHz) 0.7 0.87 fCPU = fMASTER/128 = 15.625 kHz HSI RC osc. (16MHz/8) 0.46 0.58 fCPU = fMASTER = 128 kHz LSI RC osc. (128 kHz) 0.41 0.55 fCPU = fMASTER = 16 MHz HSE user ext. clock (16 MHz) 3.9 4.
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Electrical characteristics STM8S001J3 Total current consumption in wait mode Table 21. Total current consumption in wait mode at VDD = 5 V Symbol Typ Max(1) HSE user ext. clock (16 MHz) 1.1 1.3 HSI RC osc. (16 MHz) 0.89 1.1 fCPU = fMASTER/128 = 125 kHz HSI RC osc. (16 MHz) 0.7 0.88 fCPU = fMASTER/128 = 15.625 kHz HSI RC osc. (16 MHz/8)(2) 0.45 0.57 fCPU = fMASTER = 128 kHz LSI RC osc. (128 kHz) 0.4 0.
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STM8S001J3 Electrical characteristics Total current consumption in active halt mode Table 23.
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Electrical characteristics STM8S001J3 Total current consumption in halt mode Table 25. Total current consumption in halt mode at VDD = 5 V Symbol IDD(H) Typ Max at 85°C(1) Max at 125°C(1) Flash in operating mode, HSI clock after wakeup 63 75 105 Flash in power-down mode, HSI clock after wakeup 6.0 Parameter Conditions Supply current in halt mode Unit µA 20 55 1. Guaranteed by characterization results. Table 26. Total current consumption in halt mode at VDD = 3.
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STM8S001J3 Electrical characteristics Total current consumption and timing in forced reset state Table 28. Total current consumption and timing in forced reset state Symbol Typ Max(1) VDD = 5 V 400 - VDD = 3.3 V 300 - - 150 Parameter Conditions IDD(R) Supply current in reset state (2) tRESETBL Reset release to vector fetch - Unit µA µs 1. Guaranteed by design. 2. Characterized with all I/Os tied to VSS.
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Electrical characteristics STM8S001J3 Current consumption curves The following figures show the typical current consumption measured with code executing in RAM. Figure 9. Typ. IDD(RUN) vs VDD, HSE user external clock, fCPU = 16 MHz Figure 10. Typ. IDD(RUN) vs fCPU, HSE user external clock, VDD = 5 V 50/84 Downloaded from Arrow.com.
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STM8S001J3 Electrical characteristics Figure 11. Typ. IDD(RUN) vs VDD, HSI RC osc, fCPU = 16 MHz Figure 12. Typ. IDD(WFI) vs. VDD HSE user external clock, fCPU = 16 MHz DocID030584 Rev 2 51/84 75 Downloaded from Arrow.com.
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Electrical characteristics STM8S001J3 Figure 13. Typ. IDD(WFI) vs. fCPU, HSE user external clock, VDD = 5 V Figure 14. Typ. IDD(WFI) vs VDD, HSI RC osc, fCPU = 16 MHz 52/84 Downloaded from Arrow.com.
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STM8S001J3 9.3.3 Electrical characteristics External clock sources and timing characteristics HSE user external clock Subject to general operating conditions for VDD and TA. Table 30. HSE user external clock characteristics Symbol Parameter fHSE_ext User external clock source frequency VHSEH(1) OSCIN input pin high level voltage VHSEL Conditions - Min Typ Max Unit 0 - 16 MHz 0.7 x VDD - VDD + 0.
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Electrical characteristics STM8S001J3 High speed internal RC oscillator (HSI) Table 31. HSI oscillator characteristics Symbol fHSI ACCHSI Parameter Conditions Min Typ Max Unit - - 16 - MHz - - 1.0(2) -2.5 - 1.
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STM8S001J3 Electrical characteristics Table 32. LSI oscillator characteristics (continued) Symbol Parameter Conditions Min Typ tsu(LSI) LSI oscillator wakeup time - - - IDD(LSI) LSI oscillator power consumption - - 5 Max 7 Unit (1) µs - µA 1. Guaranteed by design. Figure 17. Typical LSI frequency variation vs VDD @ 4 temperatures DocID030584 Rev 2 55/84 75 Downloaded from Arrow.com.
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Electrical characteristics 9.3.5 STM8S001J3 Memory characteristics RAM and hardware registers Table 33. RAM and hardware registers Symbol Parameter Conditions Min Unit VRM Data retention mode(1) Halt mode (or reset) VIT-max(2) V 1. Minimum supply voltage without losing data stored in RAM (in halt mode or under reset) or in hardware registers (only in halt mode). Guaranteed by design. 2. Refer to Table 18 on page 43 for the value of VIT-max.
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STM8S001J3 9.3.6 Electrical characteristics I/O port pin characteristics General characteristics Subject to general operating conditions for VDD and TA unless otherwise specified. All unused pins must be kept at a fixed voltage: using the output mode of the I/O for example or an external pull-up or pull-down resistor. Table 35. I/O static characteristics Symbol Parameter Min Typ Max Unit -0.3 - 0.3 x VDD V 0.7 x VDD - VDD + 0.
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Electrical characteristics STM8S001J3 Figure 18. Typical VIL and VIH vs VDD @ 4 temperatures Figure 19. Typical pull-up resistance vs VDD @ 4 temperatures 58/84 Downloaded from Arrow.com.
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STM8S001J3 Electrical characteristics Figure 20. Typical pull-up current vs VDD @ 4 temperatures 1. The pull-up is a pure resistor (slope goes through 0). Table 36. Output driving current (standard ports) Symbol VOL VOH Parameter Conditions Min Max Output low level with 8 pins sunk IIO = 10 mA, VDD = 5 V - 2 Output low level with 4 pins sunk IIO = 4 mA, VDD = 3.3 V - 1(1) Output high level with 8 pins sourced IIO = 10 mA, VDD = 5 V 2.8 - IIO = 4 mA, VDD = 3.3 V 2.
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Electrical characteristics STM8S001J3 Table 38. Output driving current (high sink ports) Symbol VOL VOH Parameter Conditions Min Max Output low level with 8 pins sunk IIO = 10 mA, VDD = 5 V - 0.8 Output low level with 4 pins sunk IIO = 10 mA, VDD = 3.3 V - 1.0(1) Output low level with 4 pins sunk IIO = 20 mA, VDD = 5 V - 1.5(1) Output high level with 8 pins sourced IIO = 10 mA, VDD = 5 V 4.0 - Output high level with 4 pins sourced IIO = 10 mA, VDD = 3.3 V 2.
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STM8S001J3 Electrical characteristics Figure 22. Typ. VOL @ VDD = 3.3 V (standard ports) Figure 23. Typ. VOL @ VDD = 5 V (true open drain ports) DocID030584 Rev 2 61/84 75 Downloaded from Arrow.com.
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Electrical characteristics STM8S001J3 Figure 24. Typ. VOL @ VDD = 3.3 V (true open drain ports) Figure 25. Typ. VOL @ VDD = 5 V (high sink ports) 62/84 Downloaded from Arrow.com.
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STM8S001J3 Electrical characteristics Figure 26. Typ. VOL @ VDD = 3.3 V (high sink ports) Figure 27. Typ. VDD - VOH @ VDD = 5 V (standard ports) DocID030584 Rev 2 63/84 75 Downloaded from Arrow.com.
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Electrical characteristics STM8S001J3 Figure 28. Typ. VDD - VOH @ VDD = 3.3 V (standard ports) Figure 29. Typ. VDD - VOH @ VDD = 5 V (high sink ports) 64/84 Downloaded from Arrow.com.
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STM8S001J3 Electrical characteristics Figure 30. Typ. VDD - VOH @ VDD = 3.3 V (high sink ports) 9.3.7 SPI serial peripheral interface Unless otherwise specified, the parameters given in Table 39 are derived from tests performed under ambient temperature, fMASTER frequency and VDD supply voltage conditions. tMASTER = 1/fMASTER. Refer to I/O port characteristics for more details on the input/output alternate function characteristics (NSS, SCK, MOSI, MISO). Table 39.
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Electrical characteristics STM8S001J3 Table 39.
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STM8S001J3 Electrical characteristics Figure 32. SPI timing diagram - slave mode and CPHA = 1(1) 166 LQSXW 6&. LQSXW W68 166 &3+$ &32/ &3+$ &32/ WK 166 WF 6&. WZ 6&.+ WZ 6&./ WK 62 WY 62 WD 62 0,62 287387 06% 287 %,7 287 WGLV 62 /6% 287 WK 6, WVX 6, 026, ,1387 WU 6&. WI 6&. 06% ,1 %,7 ,1 /6% ,1 DL E 1. Measurement points are done at CMOS levels: 0.3 VDD and 0.7 VDD. Figure 33. SPI timing diagram - master mode(1) +LJK 166 LQSXW 6&. 2XWSXW &3+$ &32/ 6&.
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Electrical characteristics 9.3.8 STM8S001J3 I2C interface characteristics Table 40. I2C characteristics Standard mode I2C Symbol Parameter Min(2) (2) Max Fast mode I2C(1) Min (2) Unit (2) Max tw(SCLL) SCL clock low time 4.7 - 1.3 - tw(SCLH) SCL clock high time 4.0 - 0.
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STM8S001J3 Electrical characteristics Figure 34. Typical application with I2C bus and timing diagram 9'' 9'' N N 670 6'$ ,ð& EXV 6&/ 6 7$57 5(3($7(' 6 7$57 6 7$57 WVX 67$ 6'$ WI 6'$ WU 6'$ WK 67$ 6&/ WZ 6&/+ WVX 6'$ WZ 6&// WU 6&/ WK 6'$ WI 6&/ WVX 67$ 672 6 723 WVX 672 DL 9 1. Measurement points are made at CMOS levels: 0.3 x VDD and 0.7 x VDD DocID030584 Rev 2 69/84 75 Downloaded from Arrow.com.
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Electrical characteristics 9.3.9 STM8S001J3 10-bit ADC characteristics Subject to general operating conditions for VDDA, fMASTER, and TA unless otherwise specified. Table 41. ADC characteristics Symbol Parameter Conditions Min Typ Max VDDA = 3 to 5.5 V 1 - 4 VDDA = 4.5 to 5.5 V 1 - 6 Unit fADC ADC clock frequency VAIN Conversion voltage range(1) - VSS - VDD V CADC Internal sample and hold capacitor - - 3 - pF fADC = 4 MHz - 0.75 - fADC = 6 MHz - 0.
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STM8S001J3 Electrical characteristics 1. Guaranteed by characterization results. 2. ADC accuracy vs. negative injection current: Injecting negative current on any of the analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to standard analog pins which may potentially inject negative current.
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Electrical characteristics STM8S001J3 Figure 35. ADC accuracy characteristics EG 1023 1022 1021 1LSB IDEAL V –V DDA SSA = ----------------------------------------1024 (2) ET 7 (3) (1) 6 5 EO 4 EL 3 ED 2 1 LSBIDEAL 1 0 1 VSSA 2 3 4 5 6 7 1021102210231024 VDDA 1. Example of an actual transfer curve. 2. The ideal transfer curve 3. End point correlation line ET = Total unadjusted error: maximum deviation between the actual and the ideal transfer curves.
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STM8S001J3 9.3.10 Electrical characteristics EMC characteristics Susceptibility tests are performed on a sample basis during product characterization. Functional EMS (electromagnetic susceptibility) While executing a simple application (toggling 2 LEDs through I/O ports), the product is stressed by two electromagnetic events until a failure occurs (indicated by the LEDs). • ESD: Electrostatic discharge (positive and negative) is applied on all pins of the device until a functional disturbance occurs.
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Electrical characteristics STM8S001J3 Electromagnetic interference (EMI) Based on a simple application running on the product (toggling two LEDs through the I/O ports), the product is monitored in terms of emission. Emission tests conform to the IEC 61967-2 standard for test software, board layout and pin loading. Table 45.
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STM8S001J3 Electrical characteristics Static latch-up Two complementary static tests are required on 10 parts to assess the latch-up performance: • A supply overvoltage (applied to each power supply pin) • A current injection (applied to each input, output and configurable I/O pin) is performed on each sample. This test conforms to the EIA/JESD 78 IC latch-up standard. For more details, refer to the application note AN1181. Table 47.
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Package information 10 STM8S001J3 Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark.
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STM8S001J3 Package information Table 48. SO8N – 8-lead 4.9 x 6 mm, plastic small outline, 150 mils body width, package mechanical data inches(1) millimeters Symbol Min. Typ. Max. Min. Typ. Max. D 4.800 4.900 5.000 0.1890 0.1929 0.1969 E 5.800 6.000 6.200 0.2283 0.2362 0.2441 E1 3.800 3.900 4.000 0.1496 0.1535 0.1575 e - 1.270 - - 0.0500 - h 0.250 - 0.500 0.0098 - 0.0197 k 0° - 8° 0° - 8° L 0.400 - 1.270 0.0157 - 0.0500 L1 - 1.040 - - 0.
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Package information STM8S001J3 Figure 39. SO8N – 8-lead 4.9 x 6 mm, plastic small outline, 150 mils body width, marking example 3URGXFW LGHQWLILFDWLRQ 6 - 5 < :: 'DWH FRGH 8QPDUNDEOH VXUIDFH 3,1 UHIHUHQFH $GGLWLRQDO LQIRUPDWLRQ 06Y Y 1. Parts marked as ES or E or accompanied by an Engineering Sample notification letter are not yet qualified and therefore not approved for use in production. ST is not responsible for any consequences resulting from such use.
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STM8S001J3 Package information Table 49. Thermal characteristics(1) Symbol ΘJA Parameter Thermal resistance junction-ambient SO8N Value Unit 102 °C/W 1. Thermal resistances are based on JEDEC JESD51-2 with 4-layer PCB in a natural convection environment. 10.2.1 Reference document JESD51-2 integrated circuits thermal test method environment conditions - natural convection (still air). Available from www.jedec.org. 10.2.
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Ordering information 11 STM8S001J3 Ordering information Figure 40. STM8S001J3 ordering information scheme(1) Example: STM8 S 001 J 3 M 3 TR Product class STM8 microcontroller Family type S = standard Sub-family type 001 = low density Pin count J = 8 pins Program memory size 3 = 8 Kbyte Package type M =SO8N Temperature range 3 = -40°C to 125°C Packing No character = tube TR = Tape and reel 1. For a list of available options (e.g.
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STM8S001J3 12 STM8 development tools STM8 development tools Development tools for the STM8 microcontrollers include the full-featured STice emulation system supported by a complete software tool package including C compiler, assembler and integrated development environment with high-level language debugger. In addition, the STM8 is to be supported by a complete range of tools including starter kits, evaluation boards and a low-cost in-circuit debugger/programmer. 12.
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STM8 development tools 12.2 STM8S001J3 Software tools STM8 development tools are supported by a complete, free software package from STMicroelectronics that includes ST Visual Develop (STVD) IDE and the ST Visual Programmer (STVP) software interface. STVD provides seamless integration of the Cosmic and Raisonance C compilers for STM8. A free version that outputs up to Kbytes of code is available. 12.2.
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STM8S001J3 13 Revision history Revision history Table 50. Document revision history Date Revision 24-May-2017 1 Initial release. 2 Updated: Section 10: Package information Figure 3: STM8S001J3 SO8N pinout Table 5: STM8S001J3 pin description Table 13: STM8S001J3 alternate function remapping bits for 8-pin devices Added: Section : Device marking for SO8N – 8-lead 4.9 x 6 mm, plastic small outline, 150 mils body width 29-Jun-2017 Changes DocID030584 Rev 2 83/84 83 Downloaded from Arrow.com.
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STM8S001J3 IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement.