Datasheet

ManualsBrandsST ManualsEmbedded Processors & ControllersMicrocontroller 8bit 8KB TSSOP

This is information on a product in full production.

August 2018 DS7147 Rev 10 1/103

STM8S003F3 STM8S003K3

Value line, 16-MHz STM8S 8-bit MCU, 8-Kbyte Flash memory,

128-byte data EEPROM, 10-bit ADC, 3 timers, UART, SPI, I²C

Datasheet - production data

Features

Core

• 16 MHz advanced STM8 core with Harvard

architecture and 3-stage pipeline

• Extended instruction set

Memories

• Program memory: 8 Kbyte Flash memory; data

retention 20 years at 55 °C after 100 cycles

• RAM: 1 Kbyte

• Data memory: 128 bytes true data EEPROM;

endurance up to 100 k write/erase cycles

Clock, reset and supply management

• 2.95 V to 5.5 V operating voltage

• Flexible clock control, 4 master clock sources

– Low-power crystal resonator oscillator

– External clock input

– Internal, user-trimmable 16 MHz RC

– Internal low-power 128 kHz RC

• Clock security system with clock monitor

• Power management

– Low-power modes (wait, active-halt, halt)

– Switch-off peripheral clocks individually

– Permanently active, low-consumption

power-on and power-down reset

Interrupt management

• Nested interrupt controller with 32 interrupts

• Up to 27 external interrupts on 6 vectors

Timers

• Advanced control timer: 16-bit, 4 CAPCOM

channels, 3 complementary outputs, dead-time

insertion and flexible synchronization

• 16-bit general purpose timer, with 3 CAPCOM

channels (IC, OC or PWM)

• 8-bit basic timer with 8-bit prescaler

• Auto wakeup timer

• Window and independent watchdog timers

Communications interfaces

• UART with clock output for synchronous

operation, SmartCard, IrDA, LIN master mode

• SPI interface up to 8 Mbit/s

• I

C interface up to 400 Kbit/s

Analog to digital converter (ADC)

• 10-bit ADC, ± 1 LSB ADC with up to 5

multiplexed channels, scan mode and analog

watchdog

I/Os

• Up to 28 I/Os on a 32-pin package including 21

high-sink outputs

• Highly robust I/O design, immune against

current injection

Development support

• Embedded single-wire interface module

(SWIM) for fast on-chip programming and non-

intrusive debugging

LQFP32

7x7 mm

TSSOP20

6.5x6.4 mm

UFQFPN20

3x3 mm

www.st.com

Downloaded from Arrow.com.

Summary of content (103 pages)

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STM8S003F3 STM8S003K3 Value line, 16-MHz STM8S 8-bit MCU, 8-Kbyte Flash memory, 128-byte data EEPROM, 10-bit ADC, 3 timers, UART, SPI, I²C Datasheet - production data Features Core • 16 MHz advanced STM8 core with Harvard architecture and 3-stage pipeline LQFP32 7x7 mm • Extended instruction set UFQFPN20 3x3 mm Timers Memories • Program memory: 8 Kbyte Flash memory; data retention 20 years at 55 °C after 100 cycles • RAM: 1 Kbyte • Data memory: 128 bytes true data EEPROM; endurance up to 100 k write/e
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Contents STM8S003F3 STM8S003K3 Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4 Product overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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STM8S003F3 STM8S003K3 Contents 6.2.1 I/O port hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 6.2.2 General hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 6.2.3 CPU/SWIM/debug module/interrupt controller registers . . . . . . . . . . . . 39 7 Interrupt vector mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 8 Option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Contents STM8S003F3 STM8S003K3 11 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 12 STM8 development tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 12.1 Emulation and in-circuit debugging tools . . . . . . . . . . . . . . . . . . . . . . . . . 99 12.2 Software tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 12.3 13 4/103 Downloaded from Arrow.com. 12.2.
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STM8S003F3 STM8S003K3 List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. Table 45. Table 46.
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List of tables Table 49. Table 50. Table 51. Table 52. Table 53. Table 54. Table 55. Table 56. 6/103 Downloaded from Arrow.com. STM8S003F3 STM8S003K3 EMI data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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STM8S003F3 STM8S003K3 List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40. Figure 41. Figure 42.
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List of figures Figure 48. Figure 49. Figure 50. Figure 51. Figure 52. Figure 53. 8/103 Downloaded from Arrow.com. STM8S003F3 STM8S003K3 TSSOP20 – 20-lead thin shrink small outline, 6.5 x 4.4 mm, 0.65 mm pitch, package footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 TSSOP20 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 UFQFPN20 - 20-lead, 3 x 3 mm, 0.
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STM8S003F3 STM8S003K3 1 Introduction Introduction This datasheet contains the description of the STM8S003F3/K3 value line features, pinout, electrical characteristics, mechanical data and ordering information. • For complete information on the STM8S microcontroller memory, registers and peripherals, please refer to the STM8S and STM8A microcontroller families reference manual (RM0016).
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Description 2 STM8S003F3 STM8S003K3 Description The STM8S003F3/K3 value line 8-bit microcontrollers offer 8 Kbytes of Flash program memory, plus integrated true data EEPROM. They are referred to as low-density devices in the STM8S microcontroller family reference manual (RM0016). The STM8S003F3/K3 value line devices provide the following benefits: performance, robustness and reduced system cost.
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STM8S003F3 STM8S003K3 3 Block diagram Block diagram Figure 1. STM8S003F3/K3 value line block diagram Reset block XTAL 1-16 MHz Clock controller Reset Reset POR RC int. 16 MHz BOR Detector RC int. 128 kHz Clock to peripherals and core Window WDG STM8 core Independent WDG Single wire debug interface Debug/SWIM 8 Kbyte program Flash 400 Kbit/s 8 Mbit/s I2C SPI LIN master SPI emul.
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Product overview 4 STM8S003F3 STM8S003K3 Product overview The following section intends to give an overview of the basic features of the STM8S003F3/K3 value line functional modules and peripherals. For more detailed information please refer to the corresponding family reference manual (RM0016). 4.1 Central processing unit STM8 The 8-bit STM8 core is designed for code efficiency and performance.
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STM8S003F3 STM8S003K3 4.2 Product overview Single wire interface module (SWIM) and debug module (DM) The single wire interface module and debug module permits non-intrusive, real-time incircuit debugging and fast memory programming. SWIM Single wire interface module for direct access to the debug module and memory programming. The interface can be activated in all device operation modes. The maximum data transmission speed is 145 byte/ms.
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Product overview STM8S003F3 STM8S003K3 The size of the UBC is programmable through the UBC option byte (Table 13), in increments of 1 page (64-byte block) by programming the UBC option byte in ICP mode. This divides the program memory into two areas: • Main program memory: 8 Kbyte minus UBC • User-specific boot code (UBC): Configurable up to 8 Kbyte The UBC area remains write-protected during in-application programming. This means that the MASS keys do not unlock the UBC area.
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STM8S003F3 STM8S003K3 4.5 Product overview Clock controller The clock controller distributes the system clock (fMASTER) coming from different oscillators to the core and the peripherals. It also manages clock gating for low power modes and ensures clock robustness. Features • Clock prescaler: To get the best compromise between speed and current consumption the clock frequency to the CPU and peripherals can be adjusted by a programmable prescaler.
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Product overview 4.6 STM8S003F3 STM8S003K3 Power management For efficient power management, the application can be put in one of four different lowpower modes. You can configure each mode to obtain the best compromise between the lowest power consumption, the fastest start-up time and available wakeup sources. 4.7 • Wait mode: In this mode, the CPU is stopped, but peripherals are kept running. The wakeup is performed by an internal or external interrupt or reset.
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STM8S003F3 STM8S003K3 Product overview Independent watchdog timer The independent watchdog peripheral can be used to resolve processor malfunctions due to hardware or software failures. It is clocked by the 128 kHz LSI internal RC clock source, and thus stays active even in case of a CPU clock failure The IWDG time base spans from 60 µs to 1 s. 4.8 4.
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Product overview 4.12 STM8S003F3 STM8S003K3 TIM4 - 8-bit basic timer • 8-bit autoreload, adjustable prescaler ratio to any power of 2 from 1 to 128 • Clock source: CPU clock • Interrupt source: 1 x overflow/update Table 3. TIM timer features Timer Counter size (bits) TIM1 16 Any integer from 1 to 65536 TIM2 16 TIM4 8 4.13 Counting CAPCOM Complem. Ext.
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STM8S003F3 STM8S003K3 4.14.
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Product overview 4.14.3 I2C • • 20/103 Downloaded from Arrow.com.
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STM8S003F3 STM8S003K3 5 Pinouts and pin descriptions Pinouts and pin descriptions Table 4.
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Pinouts and pin descriptions 5.
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STM8S003F3 STM8S003K3 Pinouts and pin descriptions Table 5. STM8S003K3 descriptions (continued) - - - - - - Digital ground - S - - - - - - - 1.
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Pinouts and pin descriptions STM8S003F3 STM8S003K3 Table 5. STM8S003K3 descriptions (continued) Main function (after reset) PP OD Speed High sink(1) Output Ext.
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STM8S003F3 STM8S003K3 5.2 Pinouts and pin descriptions STM8S003F3 TSSOP20/UFQFPN20 pinout and pin description Figure 4.
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Pinouts and pin descriptions STM8S003F3 STM8S003K3 PD2(HS)/AIN3/{TIM2_CH3] 20 19 18 17 16 PD6(HS)/AIN6/UART1_RX PD5(HS)/AIN5/UART1_TX PD3 (HS)/AIN4/TIM2_CH2/ADC_ETR PD4 (HS)/BEEP / TIM2_CH1/UART1_CK Figure 5.
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STM8S003F3 STM8S003K3 Pinouts and pin descriptions Table 6. STM8S003F3 pin description High sink(1) Speed Output Ext. interr. Type wpu Pin name floating Input UFQFPN20 TSSOP20 Pin no.
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Pinouts and pin descriptions STM8S003F3 STM8S003K3 Table 6. STM8S003F3 pin description (continued) PC4/ CLK_CCO/ TIM1_ 11 14 CH4/AIN2/ [TIM1_ CH2N] 15 16 17 18 19 High sink(1) Speed Output Ext. interr. Type wpu Pin name floating Input UFQFPN20 TSSOP20 Pin no.
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STM8S003F3 STM8S003K3 5.3 Pinouts and pin descriptions Alternate function remapping As shown in the rightmost column of the pin description table, some alternate functions can be remapped at different I/O ports by programming one of eight AFR (alternate function remap) option bits. Refer to Section 8: Option bytes. When the remapping option is active, the default alternate function is no longer available.
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Memory and register map STM8S003F3 STM8S003K3 6 Memory and register map 6.1 Memory map Figure 6. Memory map 0x00 0000 RAM (1 Kbyte) 0x00 03FF 0x00 0800 513 byte stack Reserved 0x00 4000 Data EEPROM 0x00 407F 0x00 47FF 0x00 4800 0x00 480A 0x00 480B Reserved Option bytes Reserved 0x00 4FFF 0x00 5000 GPIO and periph. reg.
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STM8S003F3 STM8S003K3 Memory and register map Table 7 lists the boundary addresses for each memory size. The top of the stack is at the RAM end address in each case. Table 7. Flash, Data EEPROM and RAM boundary addresses Memory area Size (byte) Start address End address Flash program memory 8K 0x00 8000 0x00 9FFF RAM 1K 0x00 0000 0x00 03FF Data EEPROM 128 0x00 4000 0x00 407F 6.2 Register map 6.2.1 I/O port hardware register map Table 8.
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Memory and register map STM8S003F3 STM8S003K3 Table 8.
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STM8S003F3 STM8S003K3 Memory and register map Table 9.
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Memory and register map STM8S003F3 STM8S003K3 Table 9.
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STM8S003F3 STM8S003K3 Memory and register map Table 9.
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Memory and register map STM8S003F3 STM8S003K3 Table 9.
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STM8S003F3 STM8S003K3 Memory and register map Table 9.
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Memory and register map STM8S003F3 STM8S003K3 Table 9.
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STM8S003F3 STM8S003K3 6.2.3 Memory and register map CPU/SWIM/debug module/interrupt controller registers Table 10.
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Memory and register map STM8S003F3 STM8S003K3 Table 10.
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STM8S003F3 STM8S003K3 7 Interrupt vector mapping Interrupt vector mapping Table 11. Interrupt mapping IRQ no.
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Option bytes 8 STM8S003F3 STM8S003K3 Option bytes Option bytes contain configurations for device hardware features as well as the memory protection of the device. They are stored in a dedicated block of the memory. Except for the ROP (read-out protection) byte, each option byte has to be stored twice, in a regular form (OPTx) and a complemented one (NOPTx) for redundancy. Option bytes can be modified in ICP mode (via SWIM) by accessing the EEPROM address shown in Table 12: Option bytes below.
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STM8S003F3 STM8S003K3 Option bytes Table 13. Option byte description (continued) Option byte no. Description OPT1 UBC[7:0] User boot code area 0x00: no UBC, no write-protection 0x01: Pages 0 defined as UBC, memory write-protected 0x02: Pages 0 to 1 defined as UBC, memory write-protected Page 0 and page 1 contain the interrupt vectors. ... 0x7F: Pages 0 to 126 defined as UBC, memory write-protected Other values: Pages 0 to 127 defined as UBC, memory-write protected.
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Option bytes 8.1 STM8S003F3 STM8S003K3 Alternate function remapping bits Table 14. STM8S003K3 alternate function remapping bits for 32-pin devices Description(1) Option byte number OPT2 AFR7Alternate function remapping option 7 Reserved. AFR6 Alternate function remapping option 6 0: AFR6 remapping option inactive: default alternate function(2) 1: Port D7 alternate function = TIM1_CH4.
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STM8S003F3 STM8S003K3 Option bytes Table 15. STM8S003F3 alternate function remapping bits for 20-pin devices Option byte number OPT2 Description AFR7Alternate function remapping option 7 0: AFR7 remapping option inactive: default alternate function(1) 1: Port C3 alternate function = TIM1_CH1N; port C4 alternate function = TIM1_CH2N. AFR6 Alternate function remapping option 6 Reserved. AFR5 Alternate function remapping option 5 Reserved.
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Electrical characteristics STM8S003F3 STM8S003K3 9 Electrical characteristics 9.1 Parameter conditions Unless otherwise specified, all voltages are referred to VSS. 9.1.1 Minimum and maximum values Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at TA = 25 °C and TA = TAmax (given by the selected temperature range).
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STM8S003F3 STM8S003K3 Electrical characteristics Figure 8. Pin input voltage STM8 pin VIN 9.2 Absolute maximum ratings Stresses above the absolute maximum ratings listed in Table 16: Voltage characteristics, Table 17: Current characteristics and Table 18: Thermal characteristics may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied.
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Electrical characteristics STM8S003F3 STM8S003K3 Table 17. Current characteristics Symbol Max.
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STM8S003F3 STM8S003K3 9.3 Electrical characteristics Operating conditions The device must be used in operating conditions that respect the parameters in Table 19. In addition, full account must be taken of all physical capacitor characteristics and tolerances. Table 19. General operating conditions Symbol Parameter Conditions Min Max Unit fCPU Internal CPU clock frequency - 0 16 MHz VDD Standard operating voltage - 2.95 5.
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Electrical characteristics STM8S003F3 STM8S003K3 Table 20. Operating conditions at power-up/power-down Symbol tVDD tTEMP Parameter VDD rise time rate VDD fall time rate Reset release delay (1) Conditions Min Typ Max - 2 - ∞ - 2 - ∞ VDD rising - - 1.7 ms Downloaded from Arrow.com. µs/V VIT+ Power-on reset threshold - 2.6 2.7 2.85 V VIT- Brown-out reset threshold - 2.5 2.65 2.8 V VHYS(BOR) Brown-out reset hysteresis - - 70 - mV 1.
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STM8S003F3 STM8S003K3 9.3.1 Electrical characteristics VCAP external capacitor Stabilization for the main regulator is achieved connecting an external capacitor CEXT to the VCAP pin. CEXT is specified in Table 19. Care should be taken to limit the series inductance to less than 15 nH. Figure 10. External capacitor CEXT C ESL ESR RLeak MSv36488V1 1. Legend: ESR is the equivalent series resistance and ESL is the equivalent inductance. 9.3.
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Electrical characteristics STM8S003F3 STM8S003K3 Table 21. Total current consumption with code execution in run mode at VDD = 5 V Symbol Typ Max (1) 2.3 - 2 2.35 HSI RC osc. (16 MHz) 1.7 2 HSE user ext. clock (16 MHz) 0.86 - HSI RC osc. (16 MHz) 0.7 0.87 fCPU = fMASTER/128 = 15.625 kHz HSI RC osc. (16 MHz/8) 0.46 0.58 fCPU = fMASTER = 128 kHz LSI RC osc. (128 kHz) 0.41 0.55 HSE crystal osc. (16 MHz) 4.5 - HSE user ext. clock (16 MHz) 4.3 4.75 HSI RC osc.(16 MHz) 3.7 4.5 0.
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STM8S003F3 STM8S003K3 Electrical characteristics Table 22. Total current consumption with code execution in run mode at VDD = 3.3 V Symbol Typ Max(1) 1.8 - 2 2.3 HSI RC osc. (16 MHz) 1.5 2 HSE user ext. clock (16 MHz) 0.81 - HSI RC osc. (16 MHz) 0.7 0.87 fCPU = fMASTER/128 = 15.625 kHz HSI RC osc. (16MHz/8) 0.46 0.58 fCPU = fMASTER = 128 kHz LSI RC osc. (128 kHz) 0.41 0.55 4 - HSE user ext. clock (16 MHz) 3.9 4.7 HSI RC osc. (16 MHz) 3.7 4.
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Electrical characteristics STM8S003F3 STM8S003K3 Total current consumption in wait mode Table 23. Total current consumption in wait mode at VDD = 5 V Symbol Typ Max(1) HSE crystal osc. (16 MHz) 1.6 - HSE user ext. clock (16 MHz) 1.1 1.3 HSI RC osc. (16 MHz) 0.89 1.1 fCPU = fMASTER/128 = 125 kHz HSI RC osc. (16 MHz) 0.7 0.88 fCPU = fMASTER/128 = 15.625 kHz HSI RC osc. (16 MHz/8)(2) 0.45 0.57 fCPU = fMASTER = 128 kHz LSI RC osc. (128 kHz) 0.4 0.
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STM8S003F3 STM8S003K3 Electrical characteristics Total current consumption in active halt mode Table 25.
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Electrical characteristics STM8S003F3 STM8S003K3 Total current consumption in halt mode Table 27. Total current consumption in halt mode at VDD = 5 V Symbol IDD(H) Typ Max at 85°C(1) Flash in operating mode, HSI clock after wakeup 63 75 Flash in power-down mode, HSI clock after wakeup 6.0 Parameter Conditions Supply current in halt mode Unit µA 20 1. Data based on characterization results. Table 28. Total current consumption in halt mode at VDD = 3.
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STM8S003F3 STM8S003K3 Electrical characteristics Total current consumption and timing in forced reset state Table 30. Total current consumption and timing in forced reset state Symbol Typ Max(1) VDD = 5 V 400 - VDD = 3.3 V 300 - - 150 Parameter Conditions IDD(R) Supply current in reset state (2) tRESETBL Reset pin release to vector fetch - Unit µA µs 1. Data guaranteed by design. 2. Characterized with all I/Os tied to VSS.
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Electrical characteristics STM8S003F3 STM8S003K3 Current consumption curves The following figures show the typical current consumption measured with code executing in RAM. Figure 11. Typ. IDD(RUN) vs VDD, HSE user external clock, fCPU = 16 MHz Figure 12. Typ. IDD(RUN) vs fCPU, HSE user external clock, VDD = 5 V 58/103 Downloaded from Arrow.com.
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STM8S003F3 STM8S003K3 Electrical characteristics Figure 13. Typ. IDD(RUN) vs VDD, HSI RC osc, fCPU = 16 MHz Figure 14. Typ. IDD(WFI) vs. VDD HSE user external clock, fCPU = 16MHz DS7147 Rev 10 59/103 87 Downloaded from Arrow.com.
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Electrical characteristics STM8S003F3 STM8S003K3 Figure 15. Typ. IDD(WFI) vs. fCPU, HSE user external clock, VDD = 5 V Figure 16. Typ. IDD(WFI) vs VDD, HSI RC osc, fCPU = 16 MHz 60/103 Downloaded from Arrow.com.
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STM8S003F3 STM8S003K3 9.3.3 Electrical characteristics External clock sources and timing characteristics HSE user external clock Subject to general operating conditions for VDD and TA. Table 32. HSE user external clock characteristics Symbol Parameter fHSE_ext User external clock source frequency VHSEH(1) OSCIN input pin high level voltage VHSEL(1) OSCIN input pin low level voltage ILEAK_HSE Conditions OSCIN input leakage current - Min Typ Max Unit 0 - 16 MHz 0.7 x VDD - VDD + 0.
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Electrical characteristics STM8S003F3 STM8S003K3 Table 33. HSE oscillator characteristics Symbol Parameter External high speed oscillator frequency fHSE Feedback resistor RF C(1) Recommended load capacitance IDD(HSE) (2) HSE oscillator power consumption gm Min Typ Max Unit - 1 - 16 MHz - - 220 - kΩ - - - 20 pF C = 20 pF, fOSC = 16 MHz - - 6 (startup) 1.6 (stabilized)(3) mA C = 10 pF, fOSC = 16 MHz - - 6 (startup) 1.
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STM8S003F3 STM8S003K3 Electrical characteristics HSE oscillator critical gm formula g mcrit = ( 2 × Π × f HSE ) 2 × R m ( 2Co + C ) 2 Rm: Notional resistance (see crystal specification) Lm: Notional inductance (see crystal specification) Cm: Notional capacitance (see crystal specification) Co: Shunt capacitance (see crystal specification) CL1=CL2=C: Grounded external capacitance gm >> gmcrit 9.3.4 Internal clock sources and timing characteristics Subject to general operating conditions for VDD and TA.
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Electrical characteristics STM8S003F3 STM8S003K3 Figure 19. Typical HSI frequency variation vs VDD at 4 temperatures Low speed internal RC oscillator (LSI) Subject to general operating conditions for VDD and TA. Table 35. LSI oscillator characteristics Symbol fLSI Parameter Conditions Min Typ - - Frequency Max Unit 128 - kHz µs µA tsu(LSI) LSI oscillator wakeup time - - - 7(1) IDD(LSI) LSI oscillator power consumption - - 5 - 1. Guaranteed by design. Figure 20.
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STM8S003F3 STM8S003K3 9.3.5 Electrical characteristics Memory characteristics RAM and hardware registers Table 36. RAM and hardware registers Symbol Parameter Conditions Min Unit VRM Data retention mode(1) Halt mode (or reset) VIT-max(2) V 1. Minimum supply voltage without losing data stored in RAM (in halt mode or under reset) or in hardware registers (only in halt mode). Guaranteed by design. 2. Refer to Table 20 on page 50 for the value of VIT-max.
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Electrical characteristics 9.3.6 STM8S003F3 STM8S003K3 I/O port pin characteristics General characteristics Subject to general operating conditions for VDD and TA unless otherwise specified. All unused pins must be kept at a fixed voltage: using the output mode of the I/O for example or an external pull-up or pull-down resistor. Table 38. I/O static characteristics Symbol Parameter Min Typ Max Unit -0.3 - 0.3 x VDD V 0.7 x VDD - VDD + 0.
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STM8S003F3 STM8S003K3 Electrical characteristics Figure 21. Typical VIL and VIH vs VDD @ 4 temperatures Figure 22. Typical pull-up resistance vs VDD @ 4 temperatures DS7147 Rev 10 67/103 87 Downloaded from Arrow.com.
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Electrical characteristics STM8S003F3 STM8S003K3 Figure 23. Typical pull-up current vs VDD @ 4 temperatures 1. The pull-up is a pure resistor (slope goes through 0). Table 39. Output driving current (standard ports) Symbol VOL VOH Parameter Conditions Min Max Output low level with 8 pins sunk IIO = 10 mA, VDD = 5 V - 2 Output low level with 4 pins sunk IIO = 4 mA, VDD = 3.3 V - 1(1) Output high level with 8 pins sourced IIO = 10 mA, VDD = 5 V 2.8 - IIO = 4 mA, VDD = 3.3 V 2.
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STM8S003F3 STM8S003K3 Electrical characteristics Table 41. Output driving current (high sink ports) Symbol VOL VOH Parameter Conditions Min Max Output low level with 8 pins sunk IIO = 10 mA, VDD = 5 V - 0.8 Output low level with 4 pins sunk IIO = 10 mA, VDD = 3.3 V - 1.0(1) Output low level with 4 pins sunk IIO = 20 mA, VDD = 5 V - 1.5(1) Output high level with 8 pins sourced IIO = 10 mA, VDD = 5 V 4.0 - Output high level with 4 pins sourced IIO = 10 mA, VDD = 3.3 V 2.
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Electrical characteristics STM8S003F3 STM8S003K3 Figure 25. Typ. VOL @ VDD = 3.3 V (standard ports) Figure 26. Typ. VOL @ VDD = 5 V (true open drain ports) 70/103 Downloaded from Arrow.com.
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STM8S003F3 STM8S003K3 Electrical characteristics Figure 27. Typ. VOL @ VDD = 3.3 V (true open drain ports) Figure 28. Typ. VOL @ VDD = 5 V (high sink ports) DS7147 Rev 10 71/103 87 Downloaded from Arrow.com.
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Electrical characteristics STM8S003F3 STM8S003K3 Figure 29. Typ. VOL @ VDD = 3.3 V (high sink ports) Figure 30. Typ. VDD - VOH @ VDD = 5 V (standard ports) 72/103 Downloaded from Arrow.com.
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STM8S003F3 STM8S003K3 Electrical characteristics Figure 31. Typ. VDD - VOH @ VDD = 3.3 V (standard ports) Figure 32. Typ. VDD - VOH @ VDD = 5 V (high sink ports) DS7147 Rev 10 73/103 87 Downloaded from Arrow.com.
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Electrical characteristics STM8S003F3 STM8S003K3 Figure 33. Typ. VDD - VOH @ VDD = 3.3 V (high sink ports) 74/103 Downloaded from Arrow.com.
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STM8S003F3 STM8S003K3 9.3.7 Electrical characteristics Reset pin characteristics Subject to general operating conditions for VDD and TA unless otherwise specified. Table 42.
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Electrical characteristics STM8S003F3 STM8S003K3 Figure 35. Typical NRST pull-up resistance vs VDD @ 4 temperatures Figure 36. Typical NRST pull-up current vs VDD @ 4 temperatures The reset network shown in Figure 37 protects the device against parasitic resets. The user must ensure that the level on the NRST pin can go below the VIL max. level specified in Table 38. Otherwise the reset is not taken into account internally.
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STM8S003F3 STM8S003K3 Electrical characteristics Figure 37. Recommended reset pin protection STM8 VDD RPU External reset circuit NRST Filter 0.1 μF (Optional) MSv36491V1 SPI serial peripheral interface 9.3.8 Unless otherwise specified, the parameters given in Table 43 are derived from tests performed under ambient temperature, fMASTER frequency and VDD supply voltage conditions. tMASTER = 1/fMASTER.
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Electrical characteristics STM8S003F3 STM8S003K3 3. Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put the data in Hi-Z. Figure 38. SPI timing diagram - slave mode and CPHA = 0 Figure 39.
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STM8S003F3 STM8S003K3 Electrical characteristics Figure 40. SPI timing diagram - master mode(1) High NSS input SCK Output CPHA= 0 CPOL=0 SCK Output tc(SCK) CPHA=1 CPOL=0 CPHA= 0 CPOL=1 CPHA=1 CPOL=1 tsu(MI) MISO INP UT tw(SCKH) tw(SCKL) MSB IN tr(SCK) tf(SCK) BIT6 IN LSB IN th(MI) MOSI OUTPUT MSB OUT B I T1 OUT tv(MO) LSB OUT th(MO) ai14136c 1. Measurement points are done at CMOS levels: 0.3 VDD and 0.7 VDD. DS7147 Rev 10 79/103 87 Downloaded from Arrow.com.
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Electrical characteristics 9.3.9 STM8S003F3 STM8S003K3 I2C interface characteristics Table 44. I2C characteristics Standard mode I2C Fast mode I2C(1) Symbol Parameter Min(2) Max(2) Min(2) Max(2) Unit tw(SCLL) SCL clock low time 4.7 - 1.3 - tw(SCLH) SCL clock high time 4.0 - 0.
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STM8S003F3 STM8S003K3 Electrical characteristics Figure 41. Typical application with I2C bus and timing diagram VDD VDD 4.7 kΩ 4.7 kΩ STM8 100 Ω SDA I²C bus SCL 100 Ω S TART REPEATED S TART S TART tsu(STA) SDA tf(SDA) tr(SDA) th(STA) SCL tw(SCLH) tsu(SDA) th(SDA) tw(SCLL) tr(SCL) tf(SCL) S TOP tsu(STA:STO) tsu(STO) ai17490V2 1. Measurement points are made at CMOS levels: 0.3 x VDD and 0.7 x VDD DS7147 Rev 10 81/103 87 Downloaded from Arrow.com.
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Electrical characteristics 9.3.10 STM8S003F3 STM8S003K3 10-bit ADC characteristics Subject to general operating conditions for VDDA, fMASTER, and TA unless otherwise specified. Table 45. ADC characteristics Symbol Parameter Conditions Min Typ Max VDDA = 3 to 5.5 V 1 - 4 VDDA = 4.5 to 5.5 V 1 - 6 Unit fADC ADC clock frequency VAIN Conversion voltage range(1) - VSS - VDD V CADC Internal sample and hold capacitor - - 3 - pF fADC = 4 MHz - 0.75 - fADC = 6 MHz - 0.
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STM8S003F3 STM8S003K3 Electrical characteristics 1. Data based on characterization results. 2. ADC accuracy vs. negative injection current: Injecting negative current on any of the analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to standard analog pins which may potentially inject negative current.
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Electrical characteristics STM8S003F3 STM8S003K3 Figure 42. ADC accuracy characteristics EG 1023 1022 1021 1LSB IDEAL V –V DDA SSA = ----------------------------------------1024 (2) ET 7 (3) (1) 6 5 EO 4 EL 3 ED 2 1 LSBIDEAL 1 0 1 VSSA 2 3 4 5 6 7 1021102210231024 VDDA 1. Example of an actual transfer curve. 2. The ideal transfer curve 3. End point correlation line ET = Total unadjusted error: maximum deviation between the actual and the ideal transfer curves.
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STM8S003F3 STM8S003K3 9.3.11 Electrical characteristics EMC characteristics Susceptibility tests are performed on a sample basis during product characterization. Functional EMS (electromagnetic susceptibility) While executing a simple application (toggling 2 LEDs through I/O ports), the product is stressed by two electromagnetic events until a failure occurs (indicated by the LEDs).
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Electrical characteristics STM8S003F3 STM8S003K3 Electromagnetic interference (EMI) Based on a simple application running on the product (toggling two LEDs through the I/O ports), the product is monitored in terms of emission. Emission tests conform to the IEC 61967-2 standard for test software, board layout and pin loading. Table 49.
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STM8S003F3 STM8S003K3 Electrical characteristics Static latch-up Two complementary static tests are required on 10 parts to assess the latch-up performance: • A supply overvoltage (applied to each power supply pin) • A current injection (applied to each input, output and configurable I/O pin) is performed on each sample. This test conforms to the EIA/JESD 78 IC latch-up standard. For more details, refer to the application note AN1181. Table 51.
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Package information 10 STM8S003F3 STM8S003K3 Package information To meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at www.st.com. ECOPACK® is an ST trademark. 10.1 LQFP32 package information Figure 44. LQFP32 - 32-pin, 7 x 7 mm low-profile quad flat package outline c A2 A1 A SEATING PLANE C 0.
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STM8S003F3 STM8S003K3 Package information Table 52. LQFP32 - 32-pin, 7 x 7 mm low-profile quad flat package mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A - - 1.600 - - 0.0630 A1 0.050 - 0.150 0.0020 - 0.0059 A2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.300 0.370 0.450 0.0118 0.0146 0.0177 c 0.090 - 0.200 0.0035 - 0.0079 D 8.800 9.000 9.200 0.3465 0.3543 0.3622 D1 6.800 7.000 7.200 0.2677 0.2756 0.2835 D3 - 5.600 - - 0.
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Package information STM8S003F3 STM8S003K3 Device marking for LQFP32 The following figure gives an example of topside marking orientation versus pin 1 identifier location. Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below. Figure 46. LQFP32 marking example (package top view) Product (1) identification STM8S003 K6T6C Date code Standard ST logo Y WW Revision code Pin 1 identifier R MS37767V1 1.
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STM8S003F3 STM8S003K3 10.2 Package information TSSOP20 package information Figure 47. TSSOP20 – 20-lead thin shrink small outline, 6.5 x 4.4 mm, 0.65 mm pitch, package outline D 20 11 c E1 E 1 SEATING PLANE C 0.25 mm GAUGE PLANE 10 PIN 1 IDENTIFICATION k aaa C A1 A A2 b L L1 e YA_ME_V3 1. Drawing is not to scale. Table 53. TSSOP20 – 20-lead thin shrink small outline, 6.5 x 4.4 mm, 0.65 mm pitch, package mechanical data inches(1) millimeters Symbol Min. Typ. Max. Min. Typ. Max.
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Package information STM8S003F3 STM8S003K3 Figure 48. TSSOP20 – 20-lead thin shrink small outline, 6.5 x 4.4 mm, 0.65 mm pitch, package footprint 0.25 6.25 20 11 1.35 0.25 7.10 4.40 1.35 1 10 0.40 0.65 YA_FP_V1 1. Dimensions are expressed in millimeters. Device marking for TSSOP20 The following figure gives an example of topside marking orientation versus pin 1 identifier location.
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STM8S003F3 STM8S003K3 10.3 Package information UFQFPN20 package information Figure 50. UFQFPN20 - 20-lead, 3 x 3 mm, 0.5 mm pitch, ultra thin fine pitch quad flat package outline D E Pin 1 TOP VIEW D D1 e L3 L1 ddd L2 10 5 A3 e b E1 1 E 15 20 16 A1 L5 A BOTTOM VIEW SIDE VIEW A0A5_ME_V4 1. Drawing is not to scale. Table 54. UFQFPN20 - 20-lead, 3 x3 mm, 0.5 mm pitch, ultra thin fine pitch quad flat package mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A 0.
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Package information STM8S003F3 STM8S003K3 Table 54. UFQFPN20 - 20-lead, 3 x3 mm, 0.5 mm pitch, ultra thin fine pitch quad flat package mechanical data (continued) inches(1) millimeters Symbol Min Typ Max Min Typ Max b 0.180 0.250 0.300 0.0071 0.0098 0.0118 e - 0.500 - - 0.0197 - ddd - - 0.050 - - 0.0020 1. Values in inches are converted from mm and rounded to 4 decimal digits. Figure 51. UFQFPN20 - 20-lead, 3 x 3 mm, 0.
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STM8S003F3 STM8S003K3 Package information Device marking for UFQFPN20 The following figure gives an example of topside marking orientation versus pin 1 identifier location. Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below. Figure 52. UFQFPN20 marking example (package top view) Product (1) identification S033 Date code Dot (pin 1) Y Revision code WW R MS37769V1 1.
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Package information 10.4 STM8S003F3 STM8S003K3 Thermal characteristics The maximum chip junction temperature (TJmax) must never exceed the values given in Table 19: General operating conditions.
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STM8S003F3 STM8S003K3 10.4.2 Package information Selecting the product temperature range When ordering the microcontroller, the temperature range is specified in the order code (see Figure 53: STM8S003F3/K3 value line ordering information scheme(1)). The following example shows how to calculate the temperature range needed for a given application. Assuming the following application conditions: • Maximum ambient temperature TAmax= 75 °C (measured according to JESD51-2) • IDDmax = 8 mA, VDD = 5.
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Ordering information 11 STM8S003F3 STM8S003K3 Ordering information Figure 53. STM8S003F3/K3 value line ordering information scheme(1) Example: STM8 S 003 K 3 T 6 TR Product class STM8 microcontroller Family type S = standard Sub-family type(2) 00x = Value line sub-family 003 = low density Pin count F = 20 pins K = 32 pins Program memory size 3 = 8 Kbyte Package type T = LQFP P = TSSOP U = UFQFPN Temperature range 6 = -40 °C to 85 °C Package pitch No character = 0.5 mm or 0.65 mm(3) C = 0.
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STM8S003F3 STM8S003K3 12 STM8 development tools STM8 development tools Development tools for the STM8 microcontrollers include the full-featured STice emulation system supported by a complete software tool package including C compiler, assembler and integrated development environment with high-level language debugger. In addition, the STM8 is to be supported by a complete range of tools including starter kits, evaluation boards and a low-cost in-circuit debugger/programmer. 12.
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STM8 development tools 12.2 STM8S003F3 STM8S003K3 Software tools STM8 development tools are supported by a complete, free software package from STMicroelectronics that includes ST Visual Develop (STVD) IDE and the ST Visual Programmer (STVP) software interface. STVD provides seamless integration of the Cosmic and Raisonance C compilers for STM8. A free version that outputs up to 16 Kbytes of code is available. 12.2.
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STM8S003F3 STM8S003K3 13 Revision history Revision history Table 56. Document revision history Date Revision 12-Jul-2011 1 Initial release. 2 Added NRW and tRET for data EEPROM in Table: Flash program memory and data EEPROM. Updated RPU in Table: NRST pin characteristics and Table: I/O static characteristics. Updated notes related to VCAP in Table: General operating conditions. 12-Jun-2012 3 Updated temperature condition for factory calibrated ACCHSI in Table: HSI oscillator characteristics.
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Revision history STM8S003F3 STM8S003K3 Table 56. Document revision history (continued) Date 102/103 Downloaded from Arrow.com. Revision Changes 03-May-2017 9 Updated: – All table footnotes from “Guaranteed by design, not tested in production” to “Guaranteed by design” and “Data based on characterization results, not tested in production” to “Data based on characterization results” – Section 9.
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STM8S003F3 STM8S003K3 IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement.