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STM8S105xx

Access line, 16 MHz STM8S 8-bit MCU, up to 32 Kbytes Flash,

integrated EEPROM,10-bit ADC, timers, UART, SPI, I²C

Datasheet - production data

Features

Core

• 16 MHz advanced STM8 core with Harvard

architecture and 3-stage pipeline

• Extended instruction set

Memories

• Medium-density Flash/EEPROM:

− Program memory up to 32 Kbytes; data

retention 20 years at 55°C after 10 kcycles

− Data memory up to 1 Kbytes true data

EEPROM; endurance 300 kcycles

• RAM: Up to 2 Kbytes

Clock, reset and supply management

• 2.95 V to 5.5 V operating voltage

• Flexible clock control, 4 master clock sources:

− Low power crystal resonator oscillator

− External clock input

− Internal, user-trimmable 16 MHz RC

− Internal low power 128 kHz RC

• Clock security system with clock monitor

• Power management:

− Low power modes (wait, active-halt, halt)

− Switch-off peripheral clocks individually

• Permanently active, low consumption power-on

and power-down reset

Interrupt management

• Nested interrupt controller with 32 interrupts

• Up to 37 external interrupts on 6 vectors

Timers

• 2x 16-bit general purpose timers, with 2+3

CAPCOM channels (IC, OC or PWM)

• Advanced control timer: 16-bit, 4 CAPCOM

channels, 3 complementary outputs, dead-time

insertion and flexible synchronization

• 8-bit basic timer with 8-bit prescaler

• Auto wake-up timer

• Window and independent watchdog timers

Communications interfaces

• UART with clock output for synchronous

operation, Smartcard, IrDA, LIN

• SPI interface up to 8 Mbit/s

• I

C interface up to 400 Kbit/s

Analog-to-digital converter (ADC)

• 10-bit, ±1 LSB ADC with up to 10 multiplexed

channels, scan mode and analog watchdog

I/Os

• Up to 38 I/Os on a 48-pin package including 16

high sink outputs

• Highly robust I/O design, immune against current

injection

Development support

• Embedded single wire interface module (SWIM)

for fast on-chip programming and non-intrusive

debugging

Unique ID

• 96-bit unique key for each device

Table 1: Device summary

Reference

Part number

STM8S105xx

STM8S105K4, STM8S105K6, STM8S105S4,

STM8S105S6, STM8S105C4, STM8S105C6

February 2014 DocID14771 Rev 13 1/99

This is information on a product in full production

www.st.com

Summary of content (99 pages)

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STM8S105xx Access line, 16 MHz STM8S 8-bit MCU, up to 32 Kbytes Flash, integrated EEPROM,10-bit ADC, timers, UART, SPI, I²C Datasheet - production data Timers • • • • • 2x 16-bit general purpose timers, with 2+3 CAPCOM channels (IC, OC or PWM) Advanced control timer: 16-bit, 4 CAPCOM channels, 3 complementary outputs, dead-time insertion and flexible synchronization 8-bit basic timer with 8-bit prescaler Auto wake-up timer Window and independent watchdog timers Communications interfaces Features • Cor
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Contents STM8S105xx Contents 1 Introduction ....................................................................................... 8 2 Description ........................................................................................ 9 3 Block diagram ................................................................................. 10 4 Product overview ............................................................................ 11 5 4.
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STM8S105xx 10 Contents Electrical characteristics ............................................................... 42 10.1 Parameter conditions ...................................................................... 42 10.1.1 Minimum and maximum values ........................................................ 42 10.1.2 Typical values ................................................................................... 42 10.1.3 Typical curves..............................................................
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Contents STM8S105xx 15.2 15.3 Software tools ................................................................................. 94 15.2.1 STM8 toolset .................................................................................... 94 15.2.2 C and assembly toolchains .............................................................. 95 Programming tools .......................................................................... 95 16 Revision history .................................................
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STM8S105xx List of tables List of tables Table 1: Device summary ........................................................................................................................... 1 Table 2: STM8S105xx access line features ............................................................................................... 9 Table 3: Peripheral clock gating bit assignments in CLK_PCKENR1/2 registers .................................... 14 Table 4: TIM timer features ....................................
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List of tables STM8S105xx Table 54: 32-pin low profile quad flat package mechanical data.............................................................. 82 Table 55: 32-lead ultra thin fine pitch quad flat no-lead package mechanical data ................................. 84 Table 56: 32-lead shrink plastic DIP (400 ml) package mechanical data................................................. 86 Table 57: Thermal characteristics (1) .............................................................................
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STM8S105xx List of figures List of figures Figure 1: STM8S105xx access line block diagram................................................................................... 10 Figure 2: Flash memory organization ....................................................................................................... 13 Figure 3: LQFP 48-pin pinout ................................................................................................................... 19 Figure 4: LQFP 44-pin pinout ..............
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Introduction 1 STM8S105xx Introduction This datasheet contains the description of the device features, pinout, electrical characteristics, mechanical data and ordering information. • • • • 8/99 For complete information on the STM8S microcontroller memory, registers and peripherals, please refer to the STM8S microcontroller family reference manual (RM0016). For information on programming, erasing and protection of the internal Flash memory please refer to the STM8S Flash programming manual (PM0051).
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STM8S105xx 2 Description Description The STM8S105xx access line 8-bit microcontrollers offer from 16 to 32 Kbytes Flash program memory, plus integrated true data EEPROM. They are referred to as mediumdensity devices in the STM8S microcontroller family reference manual (RM0016). All devices of the STM8S105xx access line provide the following benefits: reduced system cost, performance and robustness, short development cycles, and product longevity.
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Block diagram 3 STM8S105xx Block diagram Figure 1: STM8S105xx access line block diagram 10/99 DocID14771 Rev 13
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STM8S105xx 4 Product overview Product overview The following section intends to give an overview of the basic features of the device functional modules and peripherals. For more detailed information please refer to the corresponding family reference manual (RM0016). Central processing unit STM8 The 8-bit STM8 core is designed for code efficiency and performance.
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Product overview STM8S105xx Debug module The non-intrusive debugging module features a performance close to a full-featured emulator. Beside memory and peripherals, also CPU operation can be monitored in realtime by means of shadow registers. • • • • 4.2 Interrupt controller • • • • 4.
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STM8S105xx Product overview Figure 2: Flash memory organization Read-out protection (ROP) The read-out protection blocks reading and writing the Flash program memory and data EEPROM memory in ICP mode (and debug mode). Once the read-out protection is activated, any attempt to toggle its status triggers a global erase of the program and data memory. Even if no protection can be considered as totally unbreakable, the feature provides a very high level of protection for a general purpose microcontroller. 4.
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Product overview STM8S105xx • Startup clock: After reset, the microcontroller restarts by default with an internal 2 MHz clock (HSI/8). The prescaler ratio and clock source can be changed by the application program as soon as the code execution starts. • Clock security system (CSS): This feature can be enabled by software. If an HSE clock failure occurs, the internal RC (16 MHz/8) is automatically selected by the CSS and an interrupt can optionally be generated.
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STM8S105xx Product overview The application software must refresh the counter before time-out and during a limited time window. A reset is generated in two situations: 1. 2. Timeout: At 16 MHz CPU clock the time-out period can be adjusted between 75 µs up to 64 ms. Refresh out of window: The downcounter is refreshed before its value is lower than the one stored in the window register.
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Product overview 4.11 STM8S105xx TIM4 - 8-bit basic timer • • • 8-bit autoreload, adjustable prescaler ratio to any power of 2 from 1 to 128 Clock source: CPU clock Interrupt source: 1 x overflow/update Table 4: TIM timer features 4.12 Timer Counter size (bits) Prescaler Counting mode CAPCOM channels Complem. outputs Ext.
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STM8S105xx 4.13 Product overview Communication interfaces The following communication interfaces are implemented: • • • 4.13.1 UART2: Full feature UART, synchronous mode, SPI master mode, Smartcard mode, IrDA mode, LIN2.
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Product overview STM8S105xx • Simplex synchronous transfers on two lines with a possible bidirectional data line • Master or slave operation - selectable by hardware or software • CRC calculation • 1 byte Tx and Rx buffer • Slave/master selection input pin 4.13.
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STM8S105xx 5 Pinout and pin description Pinout and pin description Table 5: Legend/abbreviations for pinout tables Type Level Output speed Port and control configuration Reset state 5.
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Pinout and pin description STM8S105xx Figure 4: LQFP 44-pin pinout 1. 2. 3. 20/99 (HS) high sink capability. (T) True open drain (P-buffer and protection diode to VDD not implemented). [ ] alternate function remapping option (If the same alternate function is shown twice, it indicates an exclusive choice not a duplication of the function).
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STM8S105xx Pinout and pin description Figure 5: LQFP/UFQFPN 32-pin pinout 1. 2. (HS) high sink capability. [ ] alternate function remapping option (If the same alternate function is shown twice, it indicates an exclusive choice not a duplication of the function). Figure 6: SDIP 32-pin pinout 1. 2. 3. (HS) high sink capability. (T) True open drain (P-buffer and protection diode to VDD not implemented).
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Pinout and pin description STM8S105xx Table 6: Pin description for STM8S105 microcontrollers 2 7 PA1/ OSC IN I/O X X 3 3 3 8 PA2/ OSC OUT I/O X X 4 4 - - VSSIO_1 S I/O ground 5 5 4 9 VSS S Digital ground 6 6 5 10 VCAP S 1.
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Pin name Type floating wpu Ext.
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Pinout and pin description 5.1.1 STM8S105xx Alternate function remapping As shown in the rightmost column of the pin description table, some alternate functions can be remapped at different I/O ports by programming one of eight AFR (alternate function remap) option bits. When the remapping option is active, the default alternate function is no longer available. To use an alternate function, the corresponding peripheral must be enabled in the peripheral registers.
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STM8S105xx Memory and register map 6 Memory and register map 6.1 Memory map Figure 7: Memory map The following table lists the boundary addresses for each memory size. The top of the stack is at the RAM end address in each case.
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Memory and register map STM8S105xx Table 7: Flash, Data EEPROM and RAM boundary addresses Memory area Size (bytes) Start address End address Flash program memory 32K 0x00 8000 0x00 FFFF 16K 0x00 8000 0x00 BFFF RAM 2K 0x00 0000 0x00 07FF Data EEPROM 1024 0x00 4000 0x00 43FF 6.2 Register map 6.2.
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STM8S105xx Memory and register map Address Register label Register name Reset status 0x00 501A PF_IDR Port F input pin value register 0xXX 0x00 501B PF_DDR Port F data direction register 0x00 0x00 501C PF_CR1 Port F control register 1 0x00 0x00 501D PF_CR2 Port F control register 2 0x00 PG_ODR Port G data output latch register 0x00 0x00 501F PG_IDR Port G input pin value register 0xXX 0x00 5020 PG_DDR Port G data direction register 0x00 0x00 5021 PG_CR1 Port G control regis
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Memory and register map Address STM8S105xx Block Register label 0x00 5063 0x00 5064 Flash FLASH _DUKR ITC External interrupt control register 1 0x00 EXTI_CR2 External interrupt control register 2 0x00 Reserved area (17 bytes) RST RST_SR 0x00 50B4 to 0x00 50BF CLK 0xXX (1) CLK_ICKR Internal clock control register 0x01 CLK_ECKR External clock control register 0x00 0x00 50C2 Reserved area (1 byte) CLK CLK_CMSR Clock master status register 0xE1 0x00 50C4 CLK_SWR Clock master switch
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STM8S105xx Memory and register map Address Register label Register name Reset status 0x00 50F1 AWU_APR AWU asynchronous prescaler buffer register 0x3F 0x00 50F2 AWU_TBR AWU timebase selection register 0x00 BEEP_CSR BEEP control/ status register 0x1F 0x00 50F3 Block BEEP 0x00 50F4 to 0x00 50FF 0x00 5200 Reserved area (12 bytes) SPI SPI_CR1 SPI control register 1 0x00 0x00 5201 SPI_CR2 SPI control register 2 0x00 0x00 5202 SPI_ICR SPI interrupt control register 0x00 0x00 5203
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Memory and register map Address STM8S105xx Block Register label Register name Reset status 0x00 5243 UART2_BRR2 UART2 baud rate register 2 0x00 0x00 5244 UART2_CR1 UART2 control register 1 0x00 0x00 5245 UART2_CR2 UART2 control register 2 0x00 0x00 5246 UART2_CR3 UART2 control register 3 0x00 0x00 5247 UART2_CR4 UART2 control register 4 0x00 0x00 5248 UART2_CR5 UART2 control register 5 0x00 0x00 5249 UART2_CR6 UART2 control register 6 0x00 0x00 524A UART2_GTR UART2 guard t
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STM8S105xx Memory and register map Address Block Register label Register name Reset status 0x00 5265 TIM1_CCR1H TIM1 capture/ compare register 1 high 0x00 0x00 5266 TIM1_CCR1L TIM1 capture/ compare register 1 low 0x00 0x00 5267 TIM1_CCR2H TIM1 capture/ compare register 2 high 0x00 0x00 5268 TIM1_CCR2L TIM1 capture/ compare register 2 low 0x00 0x00 5269 TIM1_CCR3H TIM1 capture/ compare register 3 high 0x00 0x00 526A TIM1_CCR3L TIM1 capture/ compare register 3 low 0x00 0x00 526B
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Memory and register map Address STM8S105xx Block Register label Register name Reset status 0x00 530F TIM2_CCR1H TIM2 capture/ compare register 1 high 0x00 0x00 5310 TIM2_CCR1L TIM2 capture/ compare register 1 low 0x00 0x00 5311 TIM2_CCR2H TIM2 capture/ compare reg.
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STM8S105xx Memory and register map Address Block Register label Register name Reset status 0x00 5342 TIM4_SR TIM4 status register 0x00 0x00 5343 TIM4_EGR TIM4 event generation register 0x00 0x00 5344 TIM4_CNTR TIM4 counter 0x00 0x00 5345 TIM4_PSCR TIM4 prescaler register 0x00 0x00 5346 TIM4_ARR TIM4 auto-reload register 0xFF 0x00 5347 to 0x00 53DF 0x00 53E0 to 0x00 53F3 Reserved area (153 bytes) ADC1 ADC _DBxR ADC data buffer registers 0x00 53F4 to 0x00 53FF 0x00 5400 0x00 Re
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Memory and register map 6.2.
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STM8S105xx Memory and register map Address Block Register label Register name Reset status register 1 0x00 7F97 DM_CR2 DM debug module control register 2 0x00 0x00 7F98 DM_CSR1 DM debug module control/status register 1 0x10 0x00 7F99 DM_CSR2 DM debug module control/status register 2 0x00 0x00 7F9A DM_ENFCTR DM enable function register 0xFF 0x00 7F9B to 0x00 7F9F Reserved area (5 bytes) Notes: (1) Accessible by debug module only DocID14771 Rev 13 35/99
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Interrupt vector mapping 7 STM8S105xx Interrupt vector mapping Table 11: Interrupt mapping IRQ no.
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STM8S105xx 8 Option bytes Option bytes Option bytes contain configurations for device hardware features as well as the memory protection of the device. They are stored in a dedicated block of the memory. Except for the ROP (read-out protection) byte, each option byte has to be stored twice, in a regular form (OPTx) and a complemented one (NOPTx) for redundancy. Option bytes can be modified in ICP mode (via SWIM) by accessing the EEPROM address shown in the table below.
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Option bytes Addr. STM8S105xx Option name 0x487F Option byte no. NOPTBL Option bits 7 6 5 4 3 2 1 0 Factory default setting NBL[7:0] Table 13: Option byte description Option byte no. Description OPT0 ROP[7:0] Memory readout protection (ROP) AAh: Enable readout protection (write access via SWIM protocol) Note: Refer to the family reference manual (RM0016) section on Flash/EEPROM memory readout protection for details.
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STM8S105xx Option bytes Option byte no. Description PRSC[1:0] AWU clock prescaler 0x: 16 MHz to 128 kHz prescaler 10: 8 MHz to 128 kHz prescaler 11: 4 MHz to 128 kHz prescaler OPT5 HSECNT[7:0]:HSE crystal oscillator stabilization time 0x00: 2048 HSE cycles 0xB4: 128 HSE cycles 0xD2: 8 HSE cycles 0xE1: 0.5 HSE cycles OPT6 Reserved OPT7 Reserved OPTBL BL[7:0] Bootloader option byte For STM8S products, this option is checked by the boot ROM code after reset.
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Option bytes STM8S105xx Option byte no. Description (1) 1: Port A3 alternate function = TIM3_CH1; port D2 alternate function TIM2_CH3. AFR0 Alternate function remapping option 0 (2) 0: AFR0 remapping option inactive: Default alternate function . 1: Port D3 alternate function = ADC_ETR. Notes: (1) (2) 40/99 Do not use more than one remapping option in the same port. Refer to pinout description.
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STM8S105xx 9 Unique ID Unique ID The devices feature a 96-bit unique device identifier which provides a reference number that is unique for any device and in any context. The 96 bits of the identifier can never be altered by the user. The unique device identifier can be read in single bytes and may then be concatenated using a custom algorithm.
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Electrical characteristics STM8S105xx 10 Electrical characteristics 10.1 Parameter conditions Unless otherwise specified, all voltages are referred to VSS. 10.1.1 Minimum and maximum values Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100 % of the devices with an ambient temperature at TA = 25 °C and TA = TAmax (given by the selected temperature range).
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STM8S105xx 10.1.5 Electrical characteristics Loading capacitor The loading conditions used for pin parameter measurement are shown in the following figure. Figure 9: Pin loading conditions 10.1.6 Pin input voltage The input voltage measurement on a pin of the device is described in the following figure. Figure 10: Pin input voltage 10.2 Absolute maximum ratings Stresses above those listed as ‘absolute maximum ratings’ may cause permanent damage to the device.
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Electrical characteristics STM8S105xx Symbol Ratings VDD| pins Min |VSSx VSS| Variations between all the different ground pins VESD Electrostatic discharge voltage Max Unit 50 see Section 13.3.12.4: "Absolute maximum ratings (electrical sensitivity)" Notes: (1) All power (VDD, VDDIO, VDDA) and ground (VSS, VSSIO, VSSA) pins must always be connected to the external power supply (2) IINJ(PIN) must never be exceeded. This is implicitly insured if VIN maximum is respected.
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STM8S105xx Electrical characteristics positive and negative injected currents (instantaneous values). These results are based on characterization with ΣIINJ(PIN) maximum current injection on four I/O port pins of the device. Table 18: Thermal characteristics 10.3 Symbol Ratings Value Unit TSTG Storage temperature range -65 to 150 °C TJ Maximum junction temperature 150 Operating conditions The device must be used in operating conditions that respect the parameters in the table below.
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Electrical characteristics STM8S105xx Figure 11: fCPUmax versus VDD Table 20: Operating conditions at power-up/power-down Symbol tVDD Parameter Conditions VDD rise time rate VDD fall time rate Min Max Unit 2.0 (1) ∞ µs/V 2.0 (1) ∞ tTEMP Reset releasedelay VIT+ Power-on reset threshold 2.65 VIT- Brown-out reset threshold 2.58 VHYS(BOR) Brown-out reset hysteresis Typ 1.7 (1) ms 2.8 2.95 V 2.7 2.88 VDD rising 70 mV Notes: (1) 10.3.
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STM8S105xx Electrical characteristics Figure 12: External capacitor CEXT 1. 10.3.2 ESR is the equivalent series resistance and ESL is the equivalent inductance. Supply current characteristics The current consumption is measured as described in Section 7.3: "Interrupt controller". 10.3.2.
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Electrical characteristics Symbol STM8S105xx Parameter Conditions Typ Max 2.0 = 2 MHz (16 MHz/8) fCPU = fMASTER/128 = 125 kHz HSI RC osc. (16 MHz) 1.35 fCPU = fMASTER/128 = 15.625 kHz HSI RC osc. (16 MHz/8) 0.75 fCPU = fMASTER = 128 kHz LSI RC osc. (128 kHz) 0.6 (1) Unit (2) Notes: (1) (2) Data based on characterization results, not tested in production. Default clock configuration measured with all peripherals off.
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STM8S105xx Electrical characteristics Symbol Parameter Conditions Typ Max 2.0 fCPU = fMASTER/128 = 125 kHz HSI RC osc. (16 MHz) 1.35 fCPU = fMASTER/128 = 15.625 kHz HSI RC osc. (16 MHz/8) 0.75 fCPU = fMASTER = 128 kHz LSI RC osc. (128 kHz) 0.6 (1) Unit Notes: (1) (2) 10.3.2.2 Data based on characterization results, not tested in production. Default clock configuration measured with all peripherals off.
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Electrical characteristics Symbol STM8S105xx Parameter Conditions Typ Max HSI RC osc. (16 MHz) 1.5 1.9 fCPU = fMASTER/128 = 125 kHz HSI RC osc. (16 MHz) 1.3 fCPU = fMASTER/128 = 15.625 kHz HSI RC osc. (16 MHz/8) (2) 0.7 fCPU = fMASTER = 128 kHz LSI RC osc. (128 kHz) 0.5 (1) Unit (16 MHz) Notes: (1) (2) 10.3.2.3 Data based on characterization results, not tested in production. Default clock configuration measured with all peripherals off.
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STM8S105xx Electrical characteristics Notes: (1) (2) (3) Data based on characterization results, not tested in production Configured by the REGAH bit in the CLK_ICKR register. Configured by the AHALT bit in the FLASH_CR1 register. Table 26: Total current consumption in active halt mode at VDD = 3.3 V Symbol IDD(AH) Parameter Conditions Typ Main voltage regulator (MVR) (2) Flash mode (3) Clock source On Operating mode HSE crystal osc. (16 MHz) 680 LSI RC osc. (128 kHz) 200 HSE crystal osc.
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Electrical characteristics STM8S105xx Table 28: Total current consumption in halt mode at VDD = 3.3 V Symbol Parameter Conditions Typ Max at 85 °C (1) Max at 125 °C (1) Unit IDD(H) Supply current in halt mode Flash in operating mode, HSI clock after wakeup 60 90 150 µA Flash in powerdown mode, HSI clock after wakeup 4.5 20 80 Notes: (1) 10.3.2.5 Data based on characterization results, not tested in production.
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STM8S105xx Electrical characteristics (6) 10.3.2.6 Plus 1 LSI clock depending on synchronization. Total current consumption and timing in forced reset state Table 30: Total current consumption and timing in forced reset state Symbol IDD(R) Parameter Supply current in reset state tRESETBL Conditions Typ VDD = 5 V 500 VDD = 3.3 V 400 (2) Reset pin release to vector fetch Max (1) Unit μA μs 150 Notes: (1) (2) 10.3.2.7 Data guaranteed by design, not tested in production.
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Electrical characteristics STM8S105xx Figure 13: Typ. IDD(RUN) vs. VDD, HSE user external clock, fCPU = 16 MHz Figure 14: Typ. IDD(RUN) vs. fCPU, HSE user external clock, VDD= 5 V Figure 15: Typ. IDD(RUN) vs.
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STM8S105xx Electrical characteristics Figure 16: Typ. IDD(WFI) vs. VDD, HSE user external clock, fCPU = 16 MHz Figure 17: Typ. IDD(WFI) vs. fCPU, HSE user external clock VDD = 5 V Figure 18: Typ. IDD(WFI) vs.
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Electrical characteristics 10.3.3 STM8S105xx External clock sources and timing characteristics HSE user external clock Subject to general operating conditions for VDD and TA. Table 32: HSE user external clock characteristics Symbol Parameter fHSE_ext Conditions Min Max User external clock source frequency 0 16 VHSEH(1) OSCIN input pin high level voltage 0.7 x VDD VDD + 0.3 V VHSEL(1) OSCIN input pin low level voltage VSS 0.
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STM8S105xx Electrical characteristics Symbol C (1) IDD(HSE) Parameter Conditions Min Typ Max Unit 20 pF C = 20 pF, fOSC = 16 MHz 6 (startup) (3) 1.6 (stabilized) mA C = 10 pF, fOSC =16 MHz 6 (startup) (3) 1.2 (stabilized) Recommended load capacitance (2) HSE oscillator power consumption gm Oscillator transconductance tSU(HSE)(4) Startup time 5 VDD is stabilized mA/V 1 ms Notes: (1) C is approximately equivalent to 2 x crystal Cload.
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Electrical characteristics 10.3.4 STM8S105xx Internal clock sources and timing characteristics Subject to general operating conditions for VDD and TA. High speed internal RC oscillator (HSI) Table 34: HSI oscillator characteristics Symbol Parameter Conditions Min Typ fHSI Frequency ACCHSI Accuracy of HSI oscillator User-trimmed with CLK_HSITRIMR register for given VDD and TA conditions (1) Accuracy of HSI oscillator (factory calibrated) VDD = 5 V, TA = 25°C (3) -1.0 1.
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STM8S105xx Electrical characteristics Figure 22: Typical HSI accuracy vs VDD @ 4 temperatures Low speed internal RC oscillator (LSI) Subject to general operating conditions for VDD and TA. Table 35: LSI oscillator characteristics Symbol Parameter Min Typ Max Unit fLSI Frequency 110 128 146 kHz tsu(LSI) LSI oscillator wakeup time IDD(LSI) LSI oscillator power consumption 7 5 (1) µs µA Notes: (1) Guaranteed by design, not tested in production.
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Electrical characteristics 10.3.5 STM8S105xx Memory characteristics RAM and hardware registers Table 36: RAM and hardware registers Symbol VRM Parameter Data retention mode (1) Conditions Min Unit Halt mode (or reset) VIT-max(2) V Notes: (1) Minimum supply voltage without losing data stored in RAM (in halt mode or under reset) or in hardware registers (only in halt mode). Guaranteed by design, not tested in production. refer to Section 7.
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STM8S105xx 10.3.6 Electrical characteristics I/O port pin characteristics General characteristics Subject to general operating conditions for VDD and TA unless otherwise specified. All unused pins must be kept at a fixed voltage: using the output mode of the I/O for example or an external pull-up or pull-down resistor.
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Electrical characteristics STM8S105xx Figure 24: Typical VIL and VIH vs VDD @ 4 temperatures Figure 25: Typical pull-up resistance vs VDD @ 4 temperatures 62/99 DocID14771 Rev 13
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STM8S105xx Electrical characteristics Figure 26: Typical pull-up current vs VDD @ 4 temperatures 1. The pull-up is a pure resistor (slope goes through 0). Table 39: Output driving current (standard ports) Symbol VOL VOH Parameter Conditions Min Output low level with four pins sunk IIO = 4 mA, VDD = 3.3 V Output low level with eight pins sunk IIO= 10 mA, VDD = 5 V Output high level with four pins sourced IIO = 4 mA, VDD = 3.3 V 2.
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Electrical characteristics Symbol STM8S105xx Parameter Conditions Min Max Unit VDD = 3.3 V VOH Output low level with eight pins sunk IIO = 10 mA, VDD = 5 V 0.9 Output low level with four pins sunk IIO = 20 mA, VDD = 5 V 1.6 (1) Output high level with four pins sourced IIO = 10 mA, VDD = 3.3 V 1.9 (1) Output high level with eight pins sourced IIO = 10 mA, VDD = 5 V 3.8 Output high level with four pins sourced IIO = 20 mA, VDD = 5 V 2.9 (1) Notes: (1) 10.3.
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STM8S105xx Electrical characteristics Figure 28: Typ. VOL @ VDD = 3.3 V (standard ports) Figure 29: Typ.
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Electrical characteristics STM8S105xx Figure 30: Typ. VOL @ VDD = 3.3 V (true open drain ports) Figure 31: Typ.
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STM8S105xx Electrical characteristics Figure 32: Typ. VOL @ VDD = 3.3 V (high sink ports) Figure 33: Typ. VDD - VOH @ VDD = 5 V (standard ports) Figure 34: Typ. VDD - VOH @ VDD = 3.
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Electrical characteristics STM8S105xx Figure 35: Typ. VDD - VOH @ VDD = 5 V (high sink ports) Figure 36: Typ. VDD - VOH @ VDD = 3.3 V (high sink ports) 10.3.8 Reset pin characteristics Subject to general operating conditions for VDD and TA unless otherwise specified. Table 42: NRST pin characteristics 68/99 Symbol Parameter Conditions Min Typ Max Unit VIL(NRST) NRST input low (1) level voltage -0.3 - 0.3 x VDD V VIH(NRST) NRST input high level voltage (1) 0.7 x VDD - VDD + 0.
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STM8S105xx Electrical characteristics Symbol Parameter tINFP(NRST) tOP(NRST) Conditions Min Typ Max NRST input not filtered pulse (3) 500 - - NRST output (3) pulse 20 15 - - Unit μs Notes: (1) (2) (3) Data based on characterization results, not tested in production. The RPU pull-up equivalent resistor is based on a resistive transistor Data guaranteed by design, not tested in production.
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Electrical characteristics STM8S105xx Figure 39: Typical NRST pull-up current vs VDD @ 4 temperatures The reset network shown in the following figure protects the device against parasitic resets. The user must ensure that the level on the NRST pin can go below VIL(NRST) max. (see Table 38: "I/O static characteristics" ), otherwise the reset is not taken into account internally.
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STM8S105xx Electrical characteristics Table 43: SPI characteristics Symbol Parameter Conditions Min Max Unit fSCK1 tc(SCK) SPI clock frequency Master mode 0 8 MHz Slave mode 0 6 tr(SCK) tf(SCK) SPI clock rise and fall time Capacitive load: C = 30 pF tsu(NSS)(1) NSS setup time Slave mode 4x tMASTER ns th(NSS)(1) NSS hold time Slave mode 70 ns tw(SCKH) (1) tw(SCKL) SCK high and low time Master mode tSCK/2 - 15 tsu(MI) (1) tsu(SI)(1) Data input setup time Master mode 5 ns
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Electrical characteristics STM8S105xx Figure 41: SPI timing diagram - slave mode and CPHA = 0 Figure 42: SPI timing diagram - slave mode and CPHA = 1(1) 1. 72/99 Measurement points are made at CMOS levels: 0.3 VDD and 0.7 VDD.
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STM8S105xx Electrical characteristics Figure 43: SPI timing diagram - master mode(1) 1. 10.3.10 Measurement points are made at CMOS levels: 0.3 VDD and 0.7 VDD. I2C interface characteristics Table 44: I2C characteristics Symbol Parameter Standard mode I2C Min (2) Max (2) Fast mode I2C (1) Min (2) Max Unit (2) tw(SCLL) SCL clock low time 4.7 1.3 μs tw(SCLH) SCL clock high time 4.0 0.
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Electrical characteristics Symbol STM8S105xx 2 Parameter Standard mode I C Min Cb (2) Max Capacitive load for each bus line (2) Fast mode I2C (1) Min (2) 400 Max Unit (2) 400 pF Notes: (1) (2) (3) 2 fMASTER, must be at least 8 MHz to achieve max fast I C speed (400kHz). 2 Data based on standard I C protocol requirement, not tested in production. The maximum hold time of the start condition has only to be met if the interface does not stretch the low time.
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STM8S105xx Electrical characteristics Symbol Parameter Conditions Min Typ Max Unit (1) VAIN Conversion voltage range (2) Devices with external VREF+/VREF- pins CADC Internal sample and hold capacitor tS(2) Sampling time tSTAB Wakeup time from standby tCONV Total conversion time (including sampling time, 10-bit resolution) VSSA VDDA V VREF- VREF+ V 3.0 pF fADC = 4 MHz 0.75 µs fADC = 6 MHz 0.5 7.0 µs fADC = 4 MHz 3.5 µs fADC = 6 MHz 2.
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Electrical characteristics STM8S105xx It is recommended to add a Schottky diode (pin to ground) to standard analog pins which may potentially inject negative current. Any positive injection current within the limits specified for IINJ(PIN) and ΣIINJ(PIN) in the I/O port pin characteristics section does not affect the ADC accuracy. Table 47: ADC accuracy with RAIN < 10 kΩ RAIN, VDDA = 3.
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STM8S105xx 3. Electrical characteristics End point correlation line ET = Total unadjusted error: maximum deviation between the actual and the ideal transfer curves. EO = Offset error: deviation between the first actual transition and the first ideal one. EG = Gain error: deviation between the last ideal transition and the last actual one. ED = Differential linearity error: maximum deviation between actual steps and the ideal one.
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Electrical characteristics STM8S105xx Prequalification trials Most of the common failures (unexpected reset and program counter corruption) can be recovered by applying a low state on the NRST pin or the oscillator pins for 1 second. To complete these trials, ESD stress can be applied directly on the device, over the range of specification values. When unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring.
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STM8S105xx Electrical characteristics 10.3.12.4 Absolute maximum ratings (electrical sensitivity) Based on two different tests (ESD and LU) using specific measurement methods, the product is stressed in order to determine its performance in terms of electrical sensitivity. For more details, refer to the application note AN1181. 10.3.12.
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Package information 11 STM8S105xx Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. 11.1 48-pin LQFP package mechanical data Figure 47: 48-pin low profile quad flat package (7 x 7) Table 52: 48-pin low profile quad flat package mechanical data Dim.
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STM8S105xx Package information Dim. L Min Typ Max Min Typ Max 0.450 0.600 0.750 0.0177 0.0236 0.0295 L1 k inches (1) mm 1.000 0° 3.5° ccc 0.0394 7.0° 0° 3.5° 0.080 7.0° 0.0031 Notes: (1) 11.2 Values in inches are converted from mm and rounded to 4 decimal digits 44-pin LQFP package mechanical data Figure 48: 44-pin low profile quad flat package Table 53: 44-pin low profile quad flat package mechanical data Dim. inches (1) mm Min Typ A Max Min Typ 1.600 A1 0.
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Package information STM8S105xx Dim. mm Min Typ inches Max Min (1) Typ E3 8.000 0.3150 e 0.800 0.0315 L 0.450 L1 k 0.600 0.750 0.0177 1.000 0.0° 3.5° ccc 0.0236 Max 0.0295 0.0394 7.0° 0.0° 3.5° 0.100 7.0° 0.0039 Notes: (1) 11.3 Values in inches are converted from mm and rounded to 4 decimal digits 32-pin LQFP package mechanical data Figure 49: 32-pin low profile quad flat package (7 x 7) Table 54: 32-pin low profile quad flat package mechanical data Dim.
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STM8S105xx Package information Dim. inches (1) mm Min Typ Max Min Typ Max E 8.800 9.000 9.200 0.3465 0.3543 0.3622 E1 6.800 7.000 7.200 0.2677 0.2756 0.2835 E3 5.600 0.2205 e 0.800 0.0315 L 0.450 L1 k ccc 0.600 0.750 0.0177 1.000 0° 3.5° 0.0236 0.0295 0.0394 7.0° 0° 0.100 3.5° 7.0° 0.
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Package information 11.4 STM8S105xx 32-lead UFQFPN package mechanical data Figure 50: 32-lead, ultra-thin, fine pitch quad flat no-lead package (5 x 5) 1. 2. 3. 4. Drawing is not to scale. All leads/pads should be soldered to the PCB to improve the lead/pad solder joint life. There is an exposed die pad on the underside of the UFQFPN package. It is recommended to connect and solder this backside pad to PCB ground. Dimensions are in millimeters.
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STM8S105xx Package information Dim. E2 Min Typ Max Min Typ Max 3.200 3.450 3.700 0.1260 0.1358 0.1457 e L ddd inches (1) mm 0.500 0.300 0.400 0.0197 0.500 0.0118 0.0157 0.080 0.0197 0.0031 Notes: (1) 11.5 Values in inches are converted from mm and rounded to 4 decimal digits.
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Package information STM8S105xx Table 56: 32-lead shrink plastic DIP (400 ml) package mechanical data Dim. inches (1) mm Min Typ Max Min Typ Max A 3.556 3.759 5.080 0.1400 0.1480 0.2000 A1 0.508 A2 3.048 3.556 4.572 0.1200 0.1400 0.1800 B 0.356 0.457 0.584 0.0140 0.0180 0.0230 B1 0.762 1.016 1.397 0.0300 0.0400 0.0550 C 0.203 0.254 0.356 0.0079 0.0100 0.0140 D 27.430 27.940 28.450 1.0799 1.1000 1.1201 E 9.906 10.410 11.050 0.3900 0.4098 0.
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STM8S105xx 12 Thermal characteristics Thermal characteristics The maximum chip junction temperature (TJmax) must never exceed the values given in Section 7.
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Thermal characteristics STM8S105xx • Maximum 8 standard I/Os used at the same time in output at low level with IOL = 10 mA, VOL= 2 V • Maximum 4 high sink I/Os used at the same time in output at low level with IOL = 20 mA, VOL= 1.5 V • Maximum 2 true open drain I/Os used at the same time in output at low level with IOL = 20 mA, VOL= 2 V PINTmax = 15 mA x 5.5 V = 82.5 mW PIOmax = (10 mA x 2 V x 8 )+(20 mA x 2 V x 2)+(20 mA x 1.5 V x 4) = 360 mW This gives: PINTmax = 82.5 mW and PIOmax 360 mW: PDmax = 82.
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STM8S105xx 13 Ordering information Ordering information Figure 52: STM8S105xx access line ordering information scheme 1. For a list of available options (e.g. memory size, package) and orderable part numbers or for further information on any aspect of this device, please go to www.st.com or contact the ST sales office nearest to you.
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STM8S105 FASTROM microcontroller option list 14 STM8S105xx STM8S105 FASTROM microcontroller option list (last update: September 2010) Customer ............................................................................................................... Address ............................................................................................................... Contact ...............................................................................................................
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STM8S105xx STM8S105 FASTROM microcontroller option list Padding value for unused program memory (check only one option) [ ] 0xFF Fixed value [ ] 0x83 TRAP instruction opcode [ ] 0x75 Illegal opcode (causes a reset when executed) OPT0 memory readout protection (check only one option) [ ] Disable or [ ] Enable OPT1 user boot code area (UBC) 0x(_ _) fill in the hexadecimal value, referring to the datasheet and the binary format below.
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STM8S105 FASTROM microcontroller option list STM8S105xx AFR4 (check only one option) [ ] 0: Remapping option inactive. Default alternate functions used. Refer to pinout description. [ ] 1: Port D7 alternate function = TIM1_CH4. AFR5 (check only one option) [ ] 0: Remapping option inactive. Default alternate functions used. Refer to pinout description.
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STM8S105xx STM8S105 FASTROM microcontroller option list OPT6 is reserved OPT7 is reserved OPTBL bootloader option byte (check only one option) Refer to the UM0560 (STM8L/S bootloader manual) for more details. [ ] Disable (00h) [ ] Enable (55h) Comments: ........................................................................................... Supply operating range in the application ........................................................................................... Notes: ..................
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STM8 development tools 15 STM8S105xx STM8 development tools Development tools for the STM8 microcontrollers include the full-featured STice emulation system supported by a complete software tool package including C compiler, assembler and integrated development environment with high-level language debugger. In addition, the STM8 is to be supported by a complete range of tools including starter kits, evaluation boards and a low-cost in-circuit debugger/programmer. 15.
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STM8S105xx STM8 development tools ST Visual Develop – Full-featured integrated development environment from ST, featuring • • • • • • Seamless integration of C and ASM toolsets Full-featured debugger Project management Syntax highlighting editor Integrated programming interface Support of advanced emulation features for STice such as code profiling and coverage ST Visual Programmer (STVP) – Easy-to-use, unlimited graphical interface allowing read, write and verify of your STM8 microcontroller’s Flash prog
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Revision history 16 STM8S105xx Revision history Table 58: Document revision history 96/99 Date Revision Changes 05-Jun2008 1 Initial release. 23-Jun2008 2 Corrected number of high sink outputs to 9 in I/Os on Section 3: "Features". Updated part numbers in Table 2: "STM8S105xx access line features". 12-Aug2008 3 Updated part numbers in Table 2: "STM8S105xx access line features". USART renamed UART1, LINUART renamed UART2.
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STM8S105xx Revision history Date Revision Changes characteristics(1)" and removed Table 57: Junction temperature range. Updated Figure 52: "STM8S105xx access line ordering information scheme". 10-Jun2009 8 Document status changed from “preliminary data” to “datasheet”. Standardized name of the VFQFPN package. Removed ‘wpu’ from I2C pins in Section 8: "Pinout and pin description" 21-Apr2010 9 Added UFQFPN32 package silhouette to the title page. Section 3: "Features": added unique ID. Section 7.
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Revision history Date STM8S105xx Revision Changes registers; replaced reserved address "0x00 5248" with the UART2_CR5. Figure 40: "Recommended reset pin protection": replaced 0.01 µF with 0.1 µF Updated Figure 44: "Typical application with I2C bus and timing diagram (1)". Updated footnote 1 in Table 46: ADC accuracy with RAIN < 10 kΩ , VDDA= 5V and Table 47: ADC accuracy with RAIN < 10 kΩ RAIN, VDDA=3.3V.
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STM8S105xx 17 Disclaimer Disclaimer Please Read Carefully Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale.