Datasheet

ManualsBrandsST ManualsIntegrated Circuits (ICs)PWM Controller, DIP, 1A, 30V

UC2842B/3B/4B/5B

UC3842B/3B/4B/5B

March 1999

HIGH PERFORMANCE CURRENT MODE PWM CONTROLLER

TRIMMED OSCILLATOR FOR PRECISE FRE-

QUENCY CONTROL

OSCILLATOR FREQUENCY GUARANTEED

AT 250kHz

CURRENT MODE OPERATION TO 500kHz

AUTOMATIC FEED FORWARD COMPENSA-

TION

LATCHING PWM FOR CYCLE-BY-CYCLE

CURRENT LIMITING

INTERNALLY TRIMMED REFERENCE WITH

UNDERVOLTAGE LOCKOUT

HIGH CURRENT TOTEM POLE OUTPUT

UNDERVOLTAGE LOCKOUT WITH HYSTER-

ESIS

LOW START-UP AND OPERATING CURRENT

DESCRIPTION

The UC384xB family of control ICs provides the nec-

essary features to implement off-line or DC to DC

fixed frequency current mode control schemes with

a minimal external parts count. Internally imple-

mented circuits include a trimmed oscillator for pre-

cise DUTY CYCLE CONTROL under voltage lock-

out featuring start-up current less than 0.5mA, a pre-

cision reference trimmed for accuracy at the error

amp input, logic to insure latched operation, a PWM

comparator which also provides current limit control,

and a totem pole output stage designed to source

or sink high peak current. The output stage, suitable

for driving N-Channel MOSFETs, is low in the off-

state.

Differences between members of this family are the

under-voltage lockout thresholds and maximum duty

cycle ranges. The UC3842B and UC3844B have

UVLO thresholds of 16V (on) and 10V (off), ideally

suited off-line applications The corresponding thresh-

olds for the UC3843B and UC3845B are 8.5 V and 7.9

V. The UC3842B and UC3843B can operate to duty

cycles approaching 100%. A range of the zero to <

50 % is obtained by the UC3844B and UC3845B by

the addition of an internal toggle flip flop which blanks

the output off every other clock cycle.

BLOCK DIAGRAM (toggle flip flop used only in UC3844B and UC3845B)

UVLO

S/R

REF

34V

INTERNAL

BIAS

VREF GOOD

LOGIC

2.50V

OSC

R1V

CURRENT

SENSE

COMPARATOR

PWM

LATCH

ERROR AMP.

GROUND

RT/CT

VFB

COMP

CURRENT

SENSE

VREF

5V 50mA

OUTPUT

D95IN331

Minidip

SO8

UC3842B

1/15

Summary of content (15 pages)

PAGE 1
UC2842B/3B/4B/5B UC3842B/3B/4B/5B ® HIGH PERFORMANCE CURRENT MODE PWM CONTROLLER . . .. . . .. .
PAGE 2
UC2842B/3B/4B/5B - UC3842B/3B/4B/5B ABSOLUTE MAXIMUM RATINGS Symbol Parameter Vi Supply Voltage (low impedance source) Vi IO Supply Voltage (Ii < 30mA) EO Output Energy (capacitive load) Value Unit 30 V Self Limiting ±1 5 Output Current Analog Inputs (pins 2, 3) A – 0.3 to 5.5 µJ V 10 1.
PAGE 3
UC2842B/3B/4B/5B - UC3842B/3B/4B/5B THERMAL DATA Symbol Rth j-amb Description Thermal Resistance Junction-ambient. Minidip SO8 Unit 100 150 °C/W max. ELECTRICAL CHARACTERISTICS ( [note 1] Unless otherwise stated, these specifications apply for -25 < Tamb < 85°C for UC284XB; 0 < Tamb < 70°C for UC384XB; Vi = 15V (note 5); RT = 10K; CT = 3.
PAGE 4
UC2842B/3B/4B/5B - UC3842B/3B/4B/5B ELECTRICAL CHARACTERISTICS (continued) Symbol Parameter Test Conditions UC284XB UC384XB Unit Min. Typ. Max. Min. Typ. Max. OUTPUT SECTION VOL VOH VOLS Output Low Level Output High Level ISINK = 20mA 0.1 0.4 0.1 0.4 V ISINK = 200mA 1.6 2.2 1.6 2.2 V ISOURCE = 20mA 13 13.5 13 13.5 V ISOURCE = 200mA 12 13.5 12 13.5 V UVLO Saturation VCC = 6V; ISINK = 1mA 0.1 1.1 0.1 1.
PAGE 5
UC2842B/3B/4B/5B - UC3842B/3B/4B/5B Figure 1: Open Loop Test Circuit. VREF RT 4.7KΩ 2N2222 100KΩ COMP 1KΩ ISENSE ADJUST 4.7KΩ 5KΩ 7 Vi 2 3 RT/CT OUTPUT 6 4 1W 1KΩ 0.1µF UC2842B ISENSE Vi 0.1µF 8 1 VFB ERROR AMP. ADJUST A VREF OUTPUT GROUND 5 CT GROUND D95IN343 High peak currents associated with capacitive loads necessitate careful grounding techniques. Timing and bypass capacitors should be connected close to pin 5 in a single point ground.
PAGE 6
UC2842B/3B/4B/5B - UC3842B/3B/4B/5B Figure 4: Oscillator Discharge Current vs. Temperature. Idischg (mA) Figure 5: Maximum Output Duty Cycle vs. Timing Resistor. D95IN336 D95IN335 Dmax (%) Vi=15V VOSC=2V 90 8.5 Idischg=7.5mA 80 Idischg=8.8mA 70 8.0 60 Vi=15V CT=3.3nF TA=25˚C 7.5 50 40 7.0 -55 -25 0 25 50 75 100 TA(˚C) Figure 6: Error Amp Open-Loop Gain and Phase vs. Frequency. D95IN337 (dB) Vi=15V VO=2V to 4V RL=100K TA=25˚C 80 Gain 60 0.
PAGE 7
UC2842B/3B/4B/5B - UC3842B/3B/4B/5B Figure 10: Output Saturation Voltagevs. Load Current. Ii (mA) D95IN341 Vi -1 -2 Source Saturation (Load to Ground) TA=25˚C TA=-40˚C D95IN342 20 Vi=15V 80µs Pulsed Load 120Hz Rate 15 UCX843/45 3 10 TA=-40˚C 2 TA=25˚C 5 1 Sink Saturation (Load to Vi) 0 0 200 400 RT=10K CT=3.3nF VFB=0V ISense=0V TA=25˚C UCX842/44 Vsat (V) Figure 11: Supply Current vs. Supply Voltage. GND 0 600 IO(mA) Figure 12: Output Waveform.
PAGE 8
UC2842B/3B/4B/5B - UC3842B/3B/4B/5B Figure 15 : Error Amp Configuration. 2.5V 1mA + VFB 2 COMP 1 Zi - Zf D95IN345 Figure 16 : Under Voltage Lockout. 7 Vi ON/OFF COMMAND TO REST OF IC ICC UC3842B UC3843B UC3844B UC3845B VON 16V 8.4V VOFF 10V 7.6V <17mA <0.5mA VOFF VON D95IN346 VCC During UVLO, the Output is low Figure 17 : Current Sense Circuit . ERROR AMPL. IS COMP R RS C 1 3 CURRENT SENSE 5 GND D95IN347 Peak current (is) is determined by the formula 1.
PAGE 9
UC2842B/3B/4B/5B - UC3842B/3B/4B/5B Figure 18 : Slope Compensation Techniques. VREG VREG 8 RT RT RT/CT IS RSLOPE 4 CT R1 8 RT/CT IS UC3842B RSLOPE ISENSE R1 3 5 RS 4 UC3842B CT ISENSE 3 5 RS GND GND D95IN348 Figure 19 : Isolated MOSFET Drive and Current Transformer Sensing. VCC Vin 7 ISOLATION BOUNDARY + 5.0Vref - VGS Waveforms + 0 - Q1 6 + S R Q 50% DC Ipk = - + 0 - V(pin 1) -1.
PAGE 10
UC2842B/3B/4B/5B - UC3842B/3B/4B/5B Figure 20 : Latched Shutdown. 4 OSC 8 R BIAS R + 1mA 2R + - 2 EA R 1 5 2N 3905 2N 3903 D95IN350 SCR must be selected for a holding current of less than 0.5mA at TA(min). The simple two transistor circuit can be used in place of the SCR as shown. All resistors are 10K. Figure 21: Error Amplifier Compensation From VO + 2.
PAGE 11
UC2842B/3B/4B/5B - UC3842B/3B/4B/5B Figure 22: External Clock Synchronization. VREF 8 R BIAS RT R 4 EXTERNAL SYNC INPUT OSC + CT 0.01µF 2R + 47Ω - 2 EA R 1 5 D95IN352 The diode clamp is required if the Sync amplitude is large enough to cause the bottom side of CT to go more than 300mV below ground Figure 23: External Duty Cycle Clamp and Multi Unit Synchronization.
PAGE 12
UC2842B/3B/4B/5B - UC3842B/3B/4B/5B Figure 24: Soft-Start Circuit 8 5Vref R + BIAS - R 4 OSC + S 1mA 2R + 2 - 1MΩ Q + EA R - 1V R 1 C 5 D95IN354 Figure 25: Soft-Start and Error Amplifier Output Duty Cycle Clamp.
PAGE 13
UC2842B/3B/4B/5B - UC3842B/3B/4B/5B mm DIM. MIN. TYP. A a1 inch MAX. MIN. TYP. 1.75 0.1 0.25 a2 MAX. 0.069 0.004 0.010 1.65 0.065 a3 0.65 0.85 0.026 0.033 b 0.35 0.48 0.014 0.019 b1 0.19 0.25 0.007 0.010 C 0.25 0.5 0.010 0.020 c1 45° (typ.) D (1) 4.8 5.0 0.189 0.197 E 5.8 6.2 0.228 0.244 e 1.27 e3 0.050 3.81 0.150 F (1) 3.8 4.0 0.15 0.157 L 0.4 1.27 0.016 0.050 M S OUTLINE AND MECHANICAL DATA 0.6 0.024 SO8 8 ° (max.
PAGE 14
UC2842B/3B/4B/5B - UC3842B/3B/4B/5B mm DIM. MIN. A TYP. inch MAX. MIN. 3.32 TYP. MAX. 0.131 a1 0.51 B 1.15 1.65 0.045 0.065 b 0.356 0.55 0.014 0.022 b1 0.204 0.304 0.008 0.012 0.020 D E 10.92 7.95 9.75 0.430 0.313 0.384 e 2.54 0.100 e3 7.62 0.300 e4 7.62 0.300 F 6.6 0.260 I 5.08 0.200 L Z 14/15 3.18 OUTLINE AND MECHANICAL DATA 3.81 1.52 0.125 0.150 0.
PAGE 15
UC2842B/3B/4B/5B - UC3842B/3B/4B/5B Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are subject to change without notice.