Datasheet

1/11November 2004
HIGH SPEED: t
PD
= 3.9 ns (TYP.) at V
CC
= 5V
LOW POWER DISSIPATION:
I
CC
= 2 µA (MAX.) at T
A
=25°C
TYPICAL HYSTERESIS:
V
h
= 1V at V
CC
= 4.5V
POWER DOWN PROTECTION ON INPUTS
SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
| = I
OL
= 8 mA (MIN)
BALANCED PROPAGATION DELAYS:
t
PLH
t
PHL
OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 2V to 5.5V
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 132
IMPROVED LATCH-UP IMMUNITY
LOW NOISE: V
OLP
= 0.8V (MAX.)
DESCRIPTION
The 74VHC132 is an advanced high-speed
CMOS QUAD 2-INPUT SCHMITT NAND GATE
fabricated with sub-micron silicon gate and
double-layer metal wiring C
2
MOS technology.
Power down protection is provided on all inputs
and 0 to 7V can be accepted on inputs with no
regard to the supply voltage. This device can be
used to interface 5V to 3V.
Pin configuration and function are the same as
those of the 74VHC00 but the 74VHC132 has
hysteresis.
This together with its schmitt trigger function
allows it to be used on line receivers with slow
rise/fall input signals.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
74VHC132
QUAD 2-INPUT SCHMITT NAND GATE
Figure 1: Pin Connection And IEC Logic Symbols
Table 1: Order Codes
PACKAGE T & R
SOP 74VHC132MTR
TSSOP 74VHC132TTR
TSSOPSOP
Rev. 4

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