Datasheet

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STE100P

10/31

6 MFPS MF Preamble Suppression

1 =Accepts management frames with pre-amble suppressed.

0 = Will not accept management frames with preamble

suppressed. The value of this bit is controlled by bit 1 of PR20.

Its default of 1 indicates that the SFEPHY1 accepts

management frame without preamble. A minimum of 32

preamble bits are required following power-on or hardware

reset. One IDLE bit is required between any two management

transactions as per IEEE 802.3u specification.

1RO

5 ANC Auto-Negotiation Completed.

0: Auto-Negotiation process is not completed.

1: Auto-Negotiation process is completed. (PR0, Bit 12 is set)

0RO

4 RF Result of remote fault detection.

0: No remote fault condition detected.

1: Remote fault condition detected.

This bit is set when the Link Partner transmits a remote fault

condition (PR5 bit 13 = 1).

0RO/LH*

3 AN Auto-Negotiation ability.

Always 1, since STE100P has the Auto-Negotiation ability.

1RO

2 LINK Link status.

0: a failure link condition occurred. (Latched until read)

1: a valid link is established.

0 RO/LL*

1 JAB Jabber detection.

1: jabber condition is detected (10Base-T only).

0RO/LH*

0 EXT Extended register supporting.

Always 1, since STE100P supports extended register

1RO

LL* = Latching Low and clear by read. LH* = Latching High and clear by read.

PR2- PID1, PHY Identifier 1

15~0 PHYID1 Part one of PHY Identifier.

Assigned to the 3

to 18

bits of the Organizationally Unique

Identifier (OUI). (The ST OUI is 0080E1 hex).

1C04h RO

PR3- PID2, PHY Identifier 2

15~10 PHYID2 Part two of PHY Identifier.

Assigned to the 19

to 24

bits of the Organizationally Unique

Identifier (OUI).

000000b RO

9~4 MODEL Model number of STE100P.

Six bits manufacture’s model number.

000001b RO

3~0 REV Revision number of STE100P.

Four bits manufacture’s revision number.

0001b RO

PR4- ANA, Auto-Negotiation Advertisement

15 NXTPG Next Page ability.

Always 0: since STE100P does not provide next page ability.

0RO

14 --- Reserved

Table 5. Register Descriptions (continued)

Bit # Name Descriptions Default Val RW Type