Datasheet

ManualsBrandsSTMICROELECTRONICS ManualsIntegrated Circuits (ICs)TSSOP 8 128 kBit 16 K x 8

This is information on a product in full production.

January 2014 DocID16892 Rev 24 1/39

M24128-BW M24128-BR

M24128-BF M24128-DF

128-Kbit serial I²C bus EEPROM

Datasheet - production data

Features

• Compatible with all I

C bus modes:

–1 MHz

– 400 kHz

– 100 kHz

• Memory array:

– 128 Kbit (16 Kbytes) of EEPROM

– Page size: 64 bytes

– Additional Write lockable page

(M24128-D order codes)

• Single supply voltage and high speed:

– 1 MHz clock from 1.7 V to 5.5 V

• Write:

– Byte Write within 5 ms

– Page Write within 5 ms

• Operating temperature range: from -40 °C up

to +85 °C

• Random and sequential Read modes

• Write protect of the whole memory array

• Enhanced ESD/Latch-Up protection

• More than 4 million Write cycles

• More than 200-year data retention

Packages

• PDIP8 ECOPACK1

• SO8 ECOPACK2

• TSSOP8 ECOPACK2

• UFDFPN8 ECOPACK2

• WLCSP ECOPACK2

SO8 (MN)

150 mil width

TSSOP8 (DW)

169 mil width

UFDFPN8

(MC)

WLCSP (CS)

www.st.com

Summary of content (39 pages)

PAGE 1
M24128-BW M24128-BR M24128-BF M24128-DF 128-Kbit serial I²C bus EEPROM Datasheet - production data Features • Compatible with all I2C bus modes: – 1 MHz – 400 kHz – 100 kHz TSSOP8 (DW) 169 mil width SO8 (MN) 150 mil width • Memory array: – 128 Kbit (16 Kbytes) of EEPROM – Page size: 64 bytes – Additional Write lockable page (M24128-D order codes) • Single supply voltage and high speed: – 1 MHz clock from 1.7 V to 5.
PAGE 2
Contents M24128-BW M24128-BR M24128-BF M24128-DF Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 Signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.1 Serial Clock (SCL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.2 Serial Data (SDA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PAGE 3
M24128-BW M24128-BR M24128-BF M24128-DF Contents 5.2.2 Current Address Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5.2.3 Sequential Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5.3 Read Identification Page (M24128-D only) . . . . . . . . . . . . . . . . . . . . . . . 20 5.4 Read the lock status (M24128-D only) . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6 Initial delivery state . . . . . . . . . .
PAGE 4
List of tables M24128-BW M24128-BR M24128-BF M24128-DF List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. 4/39 Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Device select code . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PAGE 5
M24128-BW M24128-BR M24128-BF M24128-DF List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 8-pin package connections, top view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PAGE 6
Description 1 M24128-BW M24128-BR M24128-BF M24128-DF Description The M24128 is a 128-Kbit I2C-compatible EEPROM (Electrically Erasable PROgrammable Memory) organized as 16 K × 8 bits. The M24128-BW can operate with a supply voltage from 2.5 V to 5.5 V, the M24128-BR can operate with a supply voltage from 1.8 V to 5.5 V, and the M24128-BF and M24128-DF can operate with a supply voltage from 1.7 V to 5.5 V.
PAGE 7
M24128-BW M24128-BR M24128-BF M24128-DF Description Figure 3. WLCSP connections for the M24128-DFCS6TP/K (top view, marking side, with balls on the underside) ϭ Ϯ ϯ ϭ t Ϭ dŽƉ ƐŝĚĞ ƌĞĨĞƌĞŶĐĞ s^^ s ^ ^ > Ϯ D^ϯϬϵϭϵsϮ Caution: As EEPROM cells lose their charge (and so their binary value) when exposed to ultra violet (UV) light, EEPROM dice delivered in wafer form or in WLCSP package by STMicroelectronics must never be exposed to UV light.
PAGE 8
Signal description M24128-BW M24128-BR M24128-BF M24128-DF 2 Signal description 2.1 Serial Clock (SCL) The signal applied on the SCL input is used to strobe the data available on SDA(in) and to output the data on SDA(out). 2.2 Serial Data (SDA) SDA is an input/output used to transfer data in or data out of the device. SDA(out) is an open drain output that may be wire-OR’ed with other open drain or open collector signals on the bus.
PAGE 9
M24128-BW M24128-BR M24128-BF M24128-DF 2.6 Supply voltage (VCC) 2.6.1 Operating supply voltage (VCC) Signal description Prior to selecting the memory and issuing instructions to it, a valid and stable VCC voltage within the specified [VCC(min), VCC(max)] range must be applied (see Operating conditions in Section 8: DC and AC parameters).
PAGE 10
Memory organization 3 M24128-BW M24128-BR M24128-BF M24128-DF Memory organization The memory is organized as shown below. Figure 5.
PAGE 11
M24128-BW M24128-BR M24128-BF M24128-DF 4 Device operation Device operation The device supports the I2C protocol. This is summarized in Figure 6. Any device that sends data on to the bus is defined to be a transmitter, and any device that reads the data to be a receiver. The device that controls the data transfer is known as the bus master, and the other as the slave device. A data transfer can only be initiated by the bus master, which will also provide the serial clock for synchronization.
PAGE 12
Device operation 4.1 M24128-BW M24128-BR M24128-BF M24128-DF Start condition Start is identified by a falling edge of Serial Data (SDA) while Serial Clock (SCL) is stable in the high state. A Start condition must precede any data transfer instruction. The device continuously monitors (except during a Write cycle) Serial Data (SDA) and Serial Clock (SCL) for a Start condition. 4.2 Stop condition Stop is identified by a rising edge of Serial Data (SDA) while Serial Clock (SCL) is stable and driven high.
PAGE 13
M24128-BW M24128-BR M24128-BF M24128-DF 4.5 Device operation Device addressing To start communication between the bus master and the slave device, the bus master must initiate a Start condition. Following this, the bus master sends the device select code, shown in Table 2 (on Serial Data (SDA), most significant bit first). Table 2.
PAGE 14
Instructions M24128-BW M24128-BR M24128-BF M24128-DF 5 Instructions 5.1 Write operations Following a Start condition the bus master sends a device select code with the R/W bit (RW) reset to 0. The device acknowledges this, as shown in Figure 7, and waits for two address bytes. The device responds to each address byte with an acknowledge bit, and then waits for the data byte. Table 3. Most significant address byte A15 A14 A13 A12 A11 A10 A9 A8 A1 A0 Table 4.
PAGE 15
M24128-BW M24128-BR M24128-BF M24128-DF Byte Write After the device select code and the address bytes, the bus master sends one data byte. If the addressed location is Write-protected, by Write Control (WC) being driven high, the device replies with NoAck, and the location is not modified. If, instead, the addressed location is not Write-protected, the device replies with Ack. The bus master terminates the transfer by generating a Stop condition, as shown in Figure 7. Figure 7.
PAGE 16
Instructions 5.1.2 M24128-BW M24128-BR M24128-BF M24128-DF Page Write The Page Write mode allows up to 64 bytes to be written in a single Write cycle, provided that they are all located in the same page in the memory: that is, the most significant memory address bits, A15/A6, are the same. If more bytes are sent than will fit up to the end of the page, a “roll-over” occurs, i.e. the bytes exceeding the page end are written on the same page, from location 0.
PAGE 17
M24128-BW M24128-BR M24128-BF M24128-DF 5.1.3 Instructions Write Identification Page (M24128-D only) The Identification Page (64 bytes) is an additional page which can be written and (later) permanently locked in Read-only mode. It is written by issuing the Write Identification Page instruction.
PAGE 18
Instructions 5.1.6 M24128-BW M24128-BR M24128-BF M24128-DF Minimizing Write delays by polling on ACK The maximum Write time (tw) is shown in AC characteristics tables in Section 8: DC and AC parameters, but the typical time is shorter. To make use of this, a polling sequence can be used by the bus master. The sequence, as shown in Figure 9, is: • Initial condition: a Write cycle is in progress.
PAGE 19
M24128-BW M24128-BR M24128-BF M24128-DF Read operations Read operations are performed independently of the state of the Write Control (WC) signal. After the successful completion of a Read operation, the device internal address counter is incremented by one, to point to the next byte address. For the Read instructions, after each byte read (data out), the device waits for an acknowledgment (data in) during the 9th bit time.
PAGE 20
Instructions 5.2.1 M24128-BW M24128-BR M24128-BF M24128-DF Random Address Read A dummy Write is first performed to load the address into this address counter (as shown in Figure 10) but without sending a Stop condition. Then, the bus master sends another Start condition, and repeats the device select code, with the RW bit set to 1. The device acknowledges this, and outputs the contents of the addressed byte. The bus master must not acknowledge the byte, and terminates the transfer with a Stop condition.
PAGE 21
M24128-BW M24128-BR M24128-BF M24128-DF 5.4 Initial delivery state Read the lock status (M24128-D only) The locked/unlocked status of the Identification page can be checked by transmitting a specific truncated command [Identification Page Write instruction + one data byte] to the device. The device returns an acknowledge bit if the Identification page is unlocked, otherwise a NoAck bit if the Identification page is locked.
PAGE 22
Maximum rating 7 M24128-BW M24128-BR M24128-BF M24128-DF Maximum rating Stressing the device outside the ratings listed in Table 5 may cause permanent damage to the device. These are stress ratings only, and operation of the device at these, or any other conditions outside those indicated in the operating sections of this specification, is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 5.
PAGE 23
M24128-BW M24128-BR M24128-BF M24128-DF 8 DC and AC parameters DC and AC parameters This section summarizes the operating and measurement conditions, and the DC and AC characteristics of the device. Table 6. Operating conditions (voltage range W) Symbol Min. Max. Unit Supply voltage 2.5 5.5 V TA Ambient operating temperature –40 85 °C fC Operating clock frequency - 1 MHz Min. Max. Unit Supply voltage 1.8 5.
PAGE 24
DC and AC parameters M24128-BW M24128-BR M24128-BF M24128-DF Table 10. Input parameters Parameter(1) Symbol Test condition Min. Max. Unit CIN Input capacitance (SDA) - - 8 pF CIN Input capacitance (other pins) - - 6 pF VIN < 0.3 VCC 50 - kΩ VIN > 0.7 VCC 500 - kΩ ZL ZH Input impedance (E2, E1, E0, WC)(2) 1. Characterized only, not tested in production. 2. E2, E1, E0 input impedance when the memory is selected (after a Start condition). Table 11.
PAGE 25
M24128-BW M24128-BR M24128-BF M24128-DF DC and AC parameters Table 13. DC characteristics (M24128-BW, device grade 6) Symbol Parameter ILI Input leakage current (SCL, SDA, E2, E1, E0) ILO Output leakage current ICC ICC0 ICC1 VIL VIH VOL Supply current (Read) Supply current (Write) Standby supply current Test conditions (in addition to those in Table 6) Min. Max.
PAGE 26
DC and AC parameters M24128-BW M24128-BR M24128-BF M24128-DF Table 14. DC characteristics (M24128-BR, device grade 6) Symbol Test conditions(1) (in addition to those in Table 7) Parameter Min. Max. Unit ILI Input leakage current ( E0, E1, E2, SCL, SDA) VIN = VSS or VCC, device in Standby mode - ±2 µA ILO Output leakage current SDA in Hi-Z, external voltage applied on SDA: VSS or VCC - ±2 µA VCC = 1.8 V, fc= 400 kHz - 0.8 mA fc= 1 MHz(2) - 2.
PAGE 27
M24128-BW M24128-BR M24128-BF M24128-DF DC and AC parameters Table 15. DC characteristics (M24128-BF, M24128-DF, device grade 6) Symbol Test conditions(1) (in addition to those in Table 8) Parameter Min. Max. Unit ILI Input leakage current (E0, E1, E2, SCL, SDA) VIN = VSS or VCC device in Standby mode - ±2 µA ILO Output leakage current SDA in Hi-Z, external voltage applied on SDA: VSS or VCC - ±2 µA VCC = 1.7 V, fc= 400 kHz - 0.8 mA ICC Supply current (Read) fc= 1 MHz(2) - 2.
PAGE 28
DC and AC parameters M24128-BW M24128-BR M24128-BF M24128-DF Table 16. 400 kHz AC characteristics Symbol Alt. fC fSCL Clock frequency tCHCL tHIGH tCLCH tLOW tQL1QL2(1) tF tXH1XH2 tR Parameter Min. Max.
PAGE 29
M24128-BW M24128-BR M24128-BF M24128-DF DC and AC parameters Table 17. 1 MHz AC characteristics Parameter(1) Symbol Alt. fC fSCL Clock frequency tCHCL tHIGH tCLCH tXH1XH2 tXL1XL2 Min. Max.
PAGE 30
DC and AC parameters M24128-BW M24128-BR M24128-BF M24128-DF Figure 12. Maximum Rbus value versus bus parasitic capacitance (Cbus) for an I2C bus at maximum frequency fC = 400 kHz "US LINE PULL UP RESISTOR K K½ 4HE 2 BUS X #BUS TIME CONSTANT MUST BE BELOW THE NS TIME CONSTANT LINE REPRESENTED ON THE LEFT 2 BU S § # BU S (ERE 2BUS § #BUS NS 6## 2BUS N S )£# BUS MASTER 3#, - XXX 3$! P& "US LINE CAPACITOR P& #BUS AI B Figure 13.
PAGE 31
M24128-BW M24128-BR M24128-BF M24128-DF DC and AC parameters Figure 14.
PAGE 32
Package mechanical data 9 M24128-BW M24128-BR M24128-BF M24128-DF Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. Figure 15. TSSOP8 – 8-lead thin shrink small outline, package outline 1. Drawing is not to scale. Table 18.
PAGE 33
M24128-BW M24128-BR M24128-BF M24128-DF Package mechanical data Figure 16. SO8N – 8-lead plastic small outline, 150 mils body width, package outline K [ $ $ F FFF E H PP *$8*( 3/$1( ' N ( ( / $ / 62 $ 1. Drawing is not to scale. Table 19. SO8N – 8-lead plastic small outline, 150 mils body width, package data inches (1) millimeters Symbol Typ Min Max Typ Min Max A – – 1.750 – – 0.0689 A1 – 0.100 0.250 – 0.0039 0.0098 A2 – 1.250 – – 0.
PAGE 34
Package mechanical data M24128-BW M24128-BR M24128-BF M24128-DF Figure 17. UFDFPN8 (MLP8) – package outline (UFDFPN: Ultra thin Fine pitch Dual Flat Package, No lead) Ğ D ď >ϭ >ϯ WŝŶ ϭ Ϯ < > Ϯ ĞĞĞ ϭ tͺD ĞsϮ 1. Drawing is not to scale. 2. The central pad (area E2 by D2 in the above illustration) is internally pulled to VSS. It must not be connected to any other voltage or signal line on the PCB, for example during the soldering process. Table 20.
PAGE 35
M24128-BW M24128-BR M24128-BF M24128-DF Package mechanical data Figure 18.
PAGE 36
Package mechanical data M24128-BW M24128-BR M24128-BF M24128-DF Table 21. M24128-DFCS6TP/K, WLCSP 8-bump wafer-level chip scale package mechanical data inches(1) millimeters Symbol Typ Min Max Typ Min Max A 0.540 0.500 0.580 0.0213 0.0197 0.0228 A1 0.190 – – 0.0075 – – A2 0.350 – – 0.0138 – – b 0.270 – – 0.0106 – – D 1.271 – – 0.0500 – – E 1.081 – – 0.0425 – – e 0.800 – – 0.0315 – – e1 0.693 – – 0.0273 – – e2 0.400 – – 0.0157 – – e3 0.
PAGE 37
M24128-BW M24128-BR M24128-BF M24128-DF 10 Part numbering Part numbering Table 22. Ordering information scheme Example: M24128 - D W MN 6 T P /K Device type M24 = I2C serial access EEPROM Device function 128 = 128 Kbit (16 K x 8) Device family B = Without Identification page D = With additional Identification page Operating voltage W = VCC = 2.5 V to 5.5 V R = VCC = 1.8 V to 5.5 V F = VCC = 1.7 V to 5.
PAGE 38
Revision history 11 M24128-BW M24128-BR M24128-BF M24128-DF Revision history Table 23. Document revision history Date Revision 12-Jan-2010 18 Section 4.9: ECC (error correction code) and write cycling modified. 23-Mar-2010 19 Removed PDIP package.
PAGE 39
M24128-BW M24128-BR M24128-BF M24128-DF Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale.