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Table Of Contents

This is information on a product in full production.

September 2013 DocID024020 Rev 2 1/34

M24C01/02-W M24C01/02-R

M24C02-F

1-Kbit and 2-Kbit serial I²C bus EEPROMs

Datasheet - production data

1. Not recommended for new designs

Features

• Compatible with all I

C bus modes:

– 400 kHz

– 100 kHz

• Memory array:

– 1 Kbit (128 bytes) of EEPROM

– 2 Kbit (256 bytes) of EEPROM

– Page size: 16 bytes

• Single supply voltage:

– M24C01/02-W: 2.5 V to 5.5 V

– M24C01/02-R: 1.8 V to 5.5 V

– M24C02-F: 1.7 V to 5.5 V (full temperature

range) and 1.6 V to 1.7 V (limited

temperature range)

• Write:

– Byte Write within 5 ms

– Page Write within 5 ms

• Operating temperature range: from -40 °C up

to +85 °C

• Random and sequential Read modes

• Write protect of the whole memory array

• Enhanced ESD/Latch-Up protection

• More than 4 million Write cycles

• More than 200-year data retention

• Packages:

– RoHS compliant and halogen-free

(ECOPACK

)

PDIP8 (BN)

(1)

TSSOP8 (DW)

169 mil width

UFDFPN8

(MC)

SO8 (MN)

150 mil width

www.st.com

Summary of content (34 pages)

PAGE 1
M24C01/02-W M24C01/02-R M24C02-F 1-Kbit and 2-Kbit serial I²C bus EEPROMs Datasheet - production data Features • Compatible with all I2C bus modes: – 400 kHz – 100 kHz TSSOP8 (DW) 169 mil width SO8 (MN) 150 mil width PDIP8 (BN)(1) • Memory array: – 1 Kbit (128 bytes) of EEPROM – 2 Kbit (256 bytes) of EEPROM – Page size: 16 bytes • Single supply voltage: – M24C01/02-W: 2.5 V to 5.5 V – M24C01/02-R: 1.8 V to 5.5 V – M24C02-F: 1.7 V to 5.5 V (full temperature range) and 1.6 V to 1.
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Contents M24C01/02-W M24C01/02-R M24C02-F Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 Signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.1 Serial Clock (SCL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.2 Serial Data (SDA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.
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M24C01/02-W M24C01/02-R M24C02-F Contents 6 Initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 7 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 8 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 9 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 10 Part numbering . . . . . . . . . .
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List of tables M24C01/02-W M24C01/02-R M24C02-F List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. 4/34 Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Device select code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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M24C01/02-W M24C01/02-R M24C02-F List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 8-pin package connections, top view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Block diagram . . . . . . . .
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Description 1 M24C01/02-W M24C01/02-R M24C02-F Description The M24C01(C02) is a 1(2)-Kbit I2C-compatible EEPROM (Electrically Erasable PROgrammable Memory) organized as 128 (256) × 8 bits. The M24C01/02-W can be accessed with a supply voltage from 2.5 V to 5.5 V, the M24C01/02-R can be accessed with a supply voltage from 1.8 V to 5.5 V, and the M24C02-F can be accessed either with a supply voltage from 1.7 V to 5.5 V (over the full temperature range) or with an extended supply voltage from 1.6 V to 1.
PAGE 7
M24C01/02-W M24C01/02-R M24C02-F Signal description 2 Signal description 2.1 Serial Clock (SCL) The signal applied on the SCL input is used to strobe the data available on SDA(in) and to output the data on SDA(out). 2.2 Serial Data (SDA) SDA is an input/output used to transfer data in or data out of the device. SDA(out) is an open drain output that may be wire-OR’ed with other open drain or open collector signals on the bus.
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Signal description M24C01/02-W M24C01/02-R M24C02-F 2.6 Supply voltage (VCC) 2.6.1 Operating supply voltage (VCC) Prior to selecting the memory and issuing instructions to it, a valid and stable VCC voltage within the specified [VCC(min), VCC(max)] range must be applied (see Operating conditions in Section 8: DC and AC parameters).
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M24C01/02-W M24C01/02-R M24C02-F Memory organization The memory is organized as shown below. Figure 3.
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Device operation 4 M24C01/02-W M24C01/02-R M24C02-F Device operation The device supports the I2C protocol. This is summarized in Figure 4. Any device that sends data on to the bus is defined to be a transmitter, and any device that reads the data to be a receiver. The device that controls the data transfer is known as the bus master, and the other as the slave device. A data transfer can only be initiated by the bus master, which will also provide the serial clock for synchronization.
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M24C01/02-W M24C01/02-R M24C02-F 4.1 Device operation Start condition Start is identified by a falling edge of Serial Data (SDA) while Serial Clock (SCL) is stable in the high state. A Start condition must precede any data transfer instruction. The device continuously monitors (except during a Write cycle) Serial Data (SDA) and Serial Clock (SCL) for a Start condition. 4.2 Stop condition Stop is identified by a rising edge of Serial Data (SDA) while Serial Clock (SCL) is stable and driven high.
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Device operation 4.5 M24C01/02-W M24C01/02-R M24C02-F Device addressing To start communication between the bus master and the slave device, the bus master must initiate a Start condition. Following this, the bus master sends the device select code, shown in Table 2 (on Serial Data (SDA), most significant bit first). Table 2. Device select code Device type identifier(1) Chip Enable address RW b7 b6 b5 b4 b3 b2 b1 b0 1 0 1 0 E2 E1 E0 RW 1. The most significant bit, b7, is sent first.
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M24C01/02-W M24C01/02-R M24C02-F 5 Instructions 5.1 Write operations Instructions Following a Start condition the bus master sends a device select code with the R/W bit (RW) reset to 0. The device acknowledges this, as shown in Figure 5, and waits for the address byte. The device responds to each address byte with an acknowledge bit, and then waits for the data byte. Table 3.
PAGE 14
Instructions 5.1.1 M24C01/02-W M24C01/02-R M24C02-F Byte Write After the device select code and the address byte, the bus master sends one data byte. If the addressed location is Write-protected, by Write Control (WC) being driven high, the device replies with NoAck, and the location is not modified. If, instead, the addressed location is not Write-protected, the device replies with Ack. The bus master terminates the transfer by generating a Stop condition, as shown in Figure 5. Figure 5.
PAGE 15
M24C01/02-W M24C01/02-R M24C02-F Page Write The Page Write mode allows up to 16 bytes to be written in a single Write cycle, provided that they are all located in the same page in the memory: that is, the most significant memory address bits, A8/A4, are the same. If more bytes are sent than will fit up to the end of the page, a “roll-over” occurs, i.e. the bytes exceeding the page end are written on the same page, from location 0.
PAGE 16
Instructions 5.1.3 M24C01/02-W M24C01/02-R M24C02-F Minimizing Write delays by polling on ACK The maximum Write time (tw) is shown in AC characteristics tables in Section 8: DC and AC parameters, but the typical time is shorter. To make use of this, a polling sequence can be used by the bus master. The sequence, as shown in Figure 7, is: • Initial condition: a Write cycle is in progress.
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M24C01/02-W M24C01/02-R M24C02-F Read operations Read operations are performed independently of the state of the Write Control (WC) signal. After the successful completion of a Read operation, the device internal address counter is incremented by one, to point to the next byte address. For the Read instructions, after each byte read (data out), the device waits for an acknowledgment (data in) during the 9th bit time.
PAGE 18
Initial delivery state 5.2.1 M24C01/02-W M24C01/02-R M24C02-F Random Address Read A dummy Write is first performed to load the address into this address counter (as shown in Figure 8) but without sending a Stop condition. Then, the bus master sends another Start condition, and repeats the device select code, with the RW bit set to 1. The device acknowledges this, and outputs the contents of the addressed byte.
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M24C01/02-W M24C01/02-R M24C02-F 7 Maximum rating Maximum rating Stressing the device outside the ratings listed in Table 4 may cause permanent damage to the device. These are stress ratings only, and operation of the device at these, or any other conditions outside those indicated in the operating sections of this specification, is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 4.
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DC and AC parameters 8 M24C01/02-W M24C01/02-R M24C02-F DC and AC parameters This section summarizes the operating and measurement conditions, and the DC and AC characteristics of the device. Table 5. Operating conditions (voltage range W) Symbol Min. Max. Unit Supply voltage 2.5 5.5 V TA Ambient operating temperature –40 85 °C fC Operating clock frequency - 400 kHz Min. Max. Unit Supply voltage 1.8 5.
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M24C01/02-W M24C01/02-R M24C02-F DC and AC parameters Table 9. AC measurement conditions Symbol Cbus Parameter Min. Load capacitance Max. Unit 100 SCL input rise/fall time, SDA input fall time - pF 50 ns Input levels 0.2 VCC to 0.8 VCC V Input and output timing reference levels 0.3 VCC to 0.7 VCC V Figure 9. AC measurement I/O waveform Input voltage levels Input and output Timing reference levels 0.8VCC 0.7VCC 0.3VCC 0.2VCC MS19774V1 Table 10.
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DC and AC parameters M24C01/02-W M24C01/02-R M24C02-F Table 13. DC characteristics (M24C01/02-W, device grade 6) Symbol Parameter ILI Input leakage current (SCL, SDA, E2, E1) ILO Output leakage current ICC Supply current (Read) ICC0 ICC1 Test conditions (in addition to those in Table 5 and Table 9) Min. Max. Unit VIN = VSS or VCC, device in Standby mode - ±2 µA SDA in Hi-Z, external voltage applied on SDA: VSS or VCC - ±2 µA VCC = 5.5 V, fc = 400 kHz - 1(1) mA VCC = 2.
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M24C01/02-W M24C01/02-R M24C02-F DC and AC parameters Table 14. DC characteristics (M24C01/02-R, device grade 6) Symbol Test conditions(1) (in addition to those in Table 6 and Table 9) Parameter Min. Max. Unit ILI Input leakage current (E2, E1, SCL, SDA) VIN = VSS or VCC, device in Standby mode - ±2 µA ILO Output leakage current SDA in Hi-Z, external voltage applied on SDA: VSS or VCC - ±2 µA ICC Supply current (Read) VCC = 1.8 V, fc= 400 kHz - 0.
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DC and AC parameters M24C01/02-W M24C01/02-R M24C02-F Table 15. DC characteristics (M24C02-F, device grade 6) Symbol Test conditions(1) (in addition to those in Table 7, Table 8 and Table 9) Parameter Min. Max. Unit ILI Input leakage current (E2,E1, SCL, SDA) VIN = VSS or VCC, device in Standby mode - ±2 µA ILO Output leakage current VOUT = VSS or VCC, SDA in Hi-Z, - ±2 µA ICC Supply current (Read) VCC = 1.6 V(2) or 1.7 V, fc= 400 kHz - 0.
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M24C01/02-W M24C01/02-R M24C02-F DC and AC parameters Table 16. 400 kHz AC characteristics Symbol Alt. fC fSCL Clock frequency tCHCL tHIGH tCLCH tLOW tQL1QL2(1) tF tXH1XH2 tR Parameter Min. Max.
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DC and AC parameters M24C01/02-W M24C01/02-R M24C02-F Table 17. 100 kHz AC characteristics (I2C Standard mode)(1) Symbol Alt. fC fSCL tCHCL Parameter Min. Max. Unit Clock frequency - 100 kHz tHIGH Clock pulse width high 4 - µs tCLCH tLOW Clock pulse width low 4.
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M24C01/02-W M24C01/02-R M24C02-F DC and AC parameters Figure 10. Maximum Rbus value versus bus parasitic capacitance (Cbus) for an I2C bus at maximum frequency fC = 400 kHz Bus line pull-up resistor (k ) 100 The R bus x Cbustime constant must be below the 400 ns time constant line represented on the left. R bu s × C bu s = Here Rbus × Cbus = 120 ns 40 10 VCC Rbus 0n 4k s I²C bus master SCL M24xxx SDA 1 30 pF 10 100 Bus line capacitor (pF) Cbus 1000 ai14796b Figure 11.
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Package mechanical data 9 M24C01/02-W M24C01/02-R M24C02-F Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. Figure 12. TSSOP8 – 8-lead thin shrink small outline, package outline 1. Drawing is not to scale. Table 18.
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M24C01/02-W M24C01/02-R M24C02-F Package mechanical data Figure 13. SO8N – 8-lead plastic small outline, 150 mils body width, package outline h x 45° A2 A c ccc b e 0.25 mm GAUGE PLANE D k 8 E1 E 1 L A1 L1 SO-A 1. Drawing is not to scale. Table 19. SO8N – 8-lead plastic small outline, 150 mils body width, package data inches (1) millimeters Symbol Typ Min Max Typ Min Max A – – 1.750 – – 0.0689 A1 – 0.100 0.250 – 0.0039 0.0098 A2 – 1.250 – – 0.0492 – b – 0.
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Package mechanical data M24C01/02-W M24C01/02-R M24C02-F Figure 14. PDIP8 – 8-pin plastic DIP, 0.25 mm lead frame, package outline E b2 A2 A1 b A L c e eA eB D 8 E1 1 PDIP-B 1. Drawing is not to scale. 2. Not recommended for new designs. Table 20. PDIP8 – 8-pin plastic DIP, 0.25 mm lead frame, package mechanical data inches(1) millimeters Symbol Typ. Min. Max. Typ. Min. Max. A – – 5.33 – – 0.2098 A1 – 0.38 – – 0.0150 – A2 3.30 2.92 4.95 0.1299 0.1150 0.1949 b 0.46 0.
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M24C01/02-W M24C01/02-R M24C02-F Package mechanical data Figure 15. UFDFPN8 (MLP8) – package outline (UFDFPN: Ultra thin Fine pitch Dual Flat Package, No lead) D e MC b L1 L3 Pin 1 E E2 K L A D2 eee A1 ZW_MEeV2 1. Drawing is not to scale. 2. The central pad (area E2 by D2 in the above illustration) is internally pulled to VSS. It must not be connected to any other voltage or signal line on the PCB, for example during the soldering process. Table 21.
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Part numbering 10 M24C01/02-W M24C01/02-R M24C02-F Part numbering Table 22. Ordering information scheme Example: M24C02 Device type M24 = I2C serial access EEPROM Device function C01 = 1 Kbit (128 x 8 bit) C02 = 2 Kbit (256 x 8 bit) Operating voltage W = VCC = 2.5 V to 5.5 V R = VCC = 1.8 V to 5.5 V F = VCC = 1.6 V or 1.7 V to 5.
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M24C01/02-W M24C01/02-R M24C02-F 11 Revision history Revision history Table 23. Document revision history Date 17-Dec-2012 24-Sep-2013 Revision Changes 1 New M24C01/02 datasheet resulting from splitting the previous datasheet M24C08-x M24C04-x M24C02-x M24C01-x (revision 18) into separate datasheets. Added part number M24C02-F. Updated ESD value in Table 4. Updated standby supply current values (ICCI) in Table 13, Table 14 and Table 15.
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M24C01/02-W M24C01/02-R M24C02-F Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale.