Datasheet

4.1 - STA013 REGISTERS DESCRIPTION
The STA013 device includes 128 I
2
C registers. In
this document, only the user-oriented registers
are described. The undocumented registers are
reserved. These registers must never be ac-
cessed (in Read or in Write mode). The Read-
Only registers must never be written.
The following table describes the meaning of the
abbreviations used in the I
2
C registers descrip-
tion:
Symbol Comment
NA Not Applicable
UND Undefined
NC No Charge
RO Read Only
WO Write Only
R/W Read and Write
R/WS Read, Write in specific mode
VERSION
Address: 0x00
Type: RO
MSB LSB
b7 b6 b5 b4 b3 b2 b1 b0
V8 V7 V6 V5 V4 V3 V2 V1
The VERSION register is read-only and it is used
to identify the IC on the application board.
IDENT
Address: 0x01
Type: RO
Software Reset: 0xAC
Hardware Reset: 0xAC
MSB LSB
b7 b6 b5 b4 b3 b2 b1 b0
10101100
IDENT is a read-only register and is used to iden-
tify the IC on an application board. IDENT always
has the value "0xAC"
PLLCTL
Address: 0x05
Type: R/W
Software Reset: 0x21
Hardware Reset: 0x21
MSB LSB
b7 b6 b5 b4 b3 b2 b1 b0
XTO_
BUF
XTOD
IS
OCLK
EN
SYS2O
CLK
PPLD
IS
XTI2DS
PCLK
XTI2O
CLK
UPD_F
RAC
UPD_FRAC:
when is set to 1, update FRAC in
the switching circuit. It is set to 1 after autoboot.
XTI2OCLK:
when is set to 1, use the XTI as input
of the divider X instead of VCO output. It is set to
0 on HW reset.
XTI2DSPCLK:
when is to 1, set use the XTI as in-
put of the divider S instead of VCO output. It is
set to 0 on HW reset.
PLLDIS:
when set to 1, the VCO output is dis-
abled. It is set to 0 on HW reset.
SYS2OCLK:
when is set to 1, the OCLK fre-
quency is equal to the system frequency. It is
useful for testing. It is set to 0 on HW reset.
OCLKEN:
when is set to 1, the OCLK pad is en-
able as output pad. It is set to 1 on HW reset.
XTODIS:
when is set to 1, the XTO pad is dis-
able. It is set to 0 on HW reset.
XTO_BUF:
when this bit is set, the pin nr. 28
(OUT_CLOCK/DATA_REQ) is enabled. It is set
to 0 after autoboot.
PLLCTL (M)
Address: 0x06
Type: R/W
Software Reset: 0x0C
Hardware Reset: 0x0C
PLLCTL (N)
Address: 0x07
Type: R/W
Software Reset: 0x00
Hardware Reset: 0x00
The M and N registers are used to configure the
STA013 PLL by DSP embedded software.
M and N registers are R/W type but they are
completely controlled, on STA013, by DSP soft-
ware.
REQ_POL
Address: 0x0C
Type: R/W
Software Reset: 0x01
Hardware Reset: 0x00
STA013 - STA013B - STA013T
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