Datasheet

DRA
Address: 0x48
Type: R/W
Software Reset: 0X00
Hardware Reset: 0X00
MSB LSB
b7 b6 b5 b4 b3 b2 b1 b0 Description
DRA7 DRA6 DRA5 DRA4 DRA3 DRA2 DRA1 DRA0 OUTPUT ATTENUATION
00000000 NO ATTENUATION
00000001 -1dB
00000010 -2dB
:::::::: :
01100000 -96dB
DRA register is used to attenuate the level of
audio output at the Right Channel using the but-
terfly shown in Fig. 11. When the register is set to
255 (0xFF), the maximum attenuation is
achieved.
A decimal unit correspond to an attenuation step
of 1 dB.
DRB
Address: 0x49
Type: R/W
Software Reset: 0xFF
Hardware Reset: 0xFF
MSB LSB
b7 b6 b5 b4 b3 b2 b1 b0 Description
DRB7 DRB6 DRB5 DRB4 DRB3 DRB2 DRB1 DRB0 OUTPUT ATTENUATION
00000000 NO ATTENUATION
00000001 -1dB
00000010 -2dB
:::::::: :
01100000 -96dB
DRB register is used to re-direct the Right Chan-
nel on the Left, or to mix both the Channels.
Default value is 0x00, corresponding at the maxi-
mum attenuation in the re-direction channel.
MFSDF_441
Address: 0x50
Type: R/W
Software Reset: 0x00
Hardware Reset: 0x00
MSB LSB
b7 b6 b5 b4 b3 b2 b1 b0
X X X M4 M3 M2 M1 M0
This register contains the value for the PLL X
driver for the 44.1KHz reference frequency.
The VCO output frequency, when decoding
44.1KHz bitstream, is divided by (MFSDF_441 +1)
PLLFRAC_441_L
Address: 0x51
Type: R/W
Software Reset: 0x00
Hardware Reset: 0x00
MSB LSB
b7 b6 b5 b4 b3 b2 b1 b0
PF7 PF6 PF5 PF4 PF3 PF2 PF1 PF0
STA013 - STA013B - STA013T
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