Datasheet

RESET
D98AU974
t
reset_low_min
5.4.5. RESET
The Reset min duration (t_reset_low_min) is 100ns
HW RESET
set
PCM OUTPUT
INTERFACE
CONFIGURATION
set
set
PCM-DIVIDER
PCM-CONF.
PLL FRAC_441_H,
PLL FRAC_441_L,
PLL FRAC_H,
PLL FRAC_L }
{
set
MFS DF_441,
MFSDF }
{
PLL
CONFIGURATION
FOR:
set
PLL CTRL
48, 44.1, 32
29, 22.05, 16
12, 11.025, 8 } KHz
• {
set
SCLK_POL
INPUT SERIAL
CLOCK POLARITY
CONFIGURATION
set
DATA_REQ_ENABLE
DATA REQUEST
PIN ENABLE
set
REQ_POL
DATA REQUEST
POLARITY
CONFIGURATION
RUN
set
• MULTIMEDIA
MODE see
{TAB 5 to TAB12}
THE OVERALL
SETTING STEPS
ARE INCLUDED IN
THE STA013
CONFIGURATION
FILE AND CAN
BE DOWNLOADED
IN ONE STEP.
STM PROVIDES
A SPECIFIC
CONFIGURATION
FILE FOR EACH
SUPPORTED
INPUT CLOCK
FREQUENCY
D98AU975
5.5. CONFIGURATION FLOW
STA013 - STA013B - STA013T
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