Datasheet

Table 9:
PLL Configuration Sequence For
14.31818MHz Input Clock
512 Oversapling Rathio
REGISTER
ADDRESS
NAME VALUE
6 reserved 11
11 reserved 3
97 MFSDF (x) 6
80 MFSDF-441 7
101 PLLFRAC-H 3
82 PLLFRAC-441-H 157
100 PLLFRAC-L 211
81 PLLFRAC-441-L 157
5 PLLCTRL 161
Table 10:
PLL Configuration Sequence For
14.7456MHz Input Clock
256 Oversapling Rathio
REGISTER
ADDRESS
NAME VALUE
6 reserved 12
11 reserved 3
97 MFSDF (x) 15
80 MFSDF-441 16
101 PLLFRAC-H 85
82 PLLFRAC-441-H 4
100 PLLFRAC-L 85
81 PLLFRAC-441-L 0
5 PLLCTRL 161
Table 11:
PLL Configuration Sequence For
14.7456MHz Input Clock
384 Oversapling Rathio
REGISTER
ADDRESS
NAME VALUE
6 reserved 10
11 reserved 3
97 MFSDF (x) 8
80 MFSDF-441 9
101 PLLFRAC-H 64
82 PLLFRAC-441-H 124
100 PLLFRAC-L 0
81 PLLFRAC-441-L 0
5 PLLCTRL 161
Table 12:
PLL Configuration Sequence For
14.7456MHz Input Clock
512 Oversapling Rathio
REGISTER
ADDRESS
NAME VALUE
6 reserved 9
11 reserved 2
97 MFSDF (x) 5
80 MFSDF-441 6
101 PLLFRAC-H 0
82 PLLFRAC-441-H 184
100 PLLFRAC-L 0
81 PLLFRAC-441-L 0
5 PLLCTRL 161
STA013 - STA013B - STA013T
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