Datasheet

ManualsBrandsSTMICROELECTRONICS ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller UFQFN 28 32-Bit 48 MHz I/O number 23

This is information on a product in full production.

November 2012 Doc ID 023683 Rev 1 1/97

STM32F050x4 STM32F050x6

Low- and medium-density advanced ARM™-based 32-bit MCU with

up to 32 Kbytes Flash, timers, ADC and comm. interfaces

Datasheet − production data

Features

■ Core: ARM 32-bit Cortex™-M0 CPU,

frequency up to 48 MHz

■ Memories

– 16 to 32 Kbytes of Flash memory

– 4 Kbytes of SRAM with HW parity checking

■ CRC calculation unit

■ Reset and supply management

– Voltage range: 2.0 V to 3.6 V

– Power-on/Power-down reset (POR/PDR)

– Programmable voltage detector (PVD)

– Low power modes: Sleep, Stop and

Standby

–V

BAT

supply for RTC and backup registers

■ Clock management

– 4 to 32 MHz crystal oscillator

– 32 kHz oscillator for RTC with calibration

– Internal 8 MHz RC with x6 PLL option

– Internal 40 kHz RC oscillator

■ Up to 39 fast I/Os

– All mappable on external interrupt vectors

– Up to 25 I/Os with 5 V tolerant capability

■ 5-channel DMA controller

■ 1 × 12-bit, 1.0 µs ADC (up to 10 channels)

– Conversion range: 0 to 3.6V

– Separate analog supply from 2.4 up to

3.6 V

■ Up to 9 timers

– 1 x 16-bit 7-channel advanced-control timer

for 6 channels PWM output, with deadtime

generation and emergency stop

– 1 x 32-bit and 1 x 16-bit timer, with up to 4

IC/OC, usable for IR control decoding

– 1 x 16-bit timer, with 2 IC/OC, 1 OCN,

deadtime generation and emergency stop

– 1 x 16-bit timer, with IC/OC and OCN,

deadtime generation, emergency stop and

modulator gate for IR control

– 1 x 16-bit timer with 1 IC/OC

– Independent and system watchdog timers

– SysTick timer: 24-bit downcounter

■ Calendar RTC with alarm and periodic wakeup

from Stop/Standby

■ Communication interfaces

– 1 x I

C interface; supporting Fast Mode

Plus (1 Mbit/s) with 20 mA current sink,

SMBus/PMBus, and wakeup from STOP

– 1 x USART supporting master synchronous

SPI and modem control; one with ISO7816

interface, LIN, IrDA capability auto baud

rate detection and wakeup feature

– 1 x SPI (18 Mbit/s) with 4 to 16

programmable bit frames, with I

S interface

multiplexed

■ Serial wire debug (SWD)

■ 96-bit unique ID

■ Extended temperature range: -40 to +105°C

Table 1. Device summary

Reference Part number

STM32F050x4

STM32F050F4, STM32F050G4, STM32F050K4,

STM32F050C4

STM32F050x6

STM32F050F6, STM32F050G6, STM32F050K6,

STM32F050C6

LQFP48 7x7 UFQFPN32 5x5

TSSOP20

UFQFPN28 4x4

www.st.com

Summary of content (97 pages)

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STM32F050x4 STM32F050x6 Low- and medium-density advanced ARM™-based 32-bit MCU with up to 32 Kbytes Flash, timers, ADC and comm. interfaces Datasheet − production data Features ■ Core: ARM 32-bit Cortex™-M0 CPU, frequency up to 48 MHz ■ Memories – 16 to 32 Kbytes of Flash memory – 4 Kbytes of SRAM with HW parity checking ■ CRC calculation unit ■ Reset and supply management – Voltage range: 2.0 V to 3.
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Contents STM32F050xx Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3 Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.1 ARM® CortexTM-M0 core with embedded Flash and SRAM . . . . . . . . . 12 3.2 Memories . . . . . . . . . . . . . . . . . . . . . . . . . .
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STM32F050xx 3.16 Contents Serial wire debug port (SW-DP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4 Pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 6 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 6.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . .
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Contents 7 STM32F050xx Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 7.1 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 7.2 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 7.2.1 Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 7.2.2 Selecting the product temperature range . . . . . . . . .
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STM32F050xx List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. Table 45. Table 46. Table 47.
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List of tables Table 48. Table 49. Table 50. Table 51. Table 52. Table 53. Table 54. Table 55. Table 56. Table 57. Table 58. Table 59. Table 60. Table 61. Table 62. Table 63. Table 64. Table 65. Table 66. 6/97 STM32F050xx NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 RAIN max for fADC = 14 MHz .
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STM32F050xx List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Block diagram . . . . . . . . . . . . . . . .
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Introduction 1 STM32F050xx Introduction This datasheet provides the ordering information and mechanical device characteristics of the STM32F050x4 and STM32F050x6 microcontrollers, hereafter referred to as STM32F050xx. This datasheet should be read in conjunction with the STM32F0xxxx reference manual (RM0091). The reference manual is available from the STMicroelectronics website www.st.com.
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STM32F050xx 2 Description Description The STM32F050xx family incorporates the high-performance ARM Cortex™-M0 32-bit RISC core operating at a 48 MHz maximum frequency, high-speed embedded memories (Flash memory up to 32 Kbytes and SRAM up to 4 Kbytes), and an extensive range of enhanced peripherals and I/Os.
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Description Table 2. STM32F050xx STM32F050xx family device features and peripheral counts Peripheral Flash (Kbytes) SRAM (Kbytes) STM32F050Fx 16 32 4 STM32F050Gx 16 32 16 4 Advanced control 1 (16-bit) General purpose 4 (16-bit) 1 (32-bit) SPI (I2S)(1) I C 1 USART 1 GPIOs 1 (9 ext. + 3 int.) 15 23 27 39 2.0 to 3.6 V Ambient operating temperature: -40 °C to 85 °C / -40 °C to 105 °C Junction temperature: -40°C to 105°C / -40 °C to 125 °C TSSOP20 UFQFPN28 1.
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STM32F050xx 3ERIAL 7IRE $EBUG 6$$ FLASH OBL )NTERFACE 37#,+ 37$!4 AS !& Block diagram .6)# '0 $-! CHANNELS "US-ATRIX .6)# 32!- #/24%8 - #05 F(#,+ -(Z CONTROLLER Figure 1. Description 0/7%2 6/,4 2%' 6 4/ 6 &,!3( +" BITS 6$$ TO 6 633 6$$ 0/2 2ESET 32! +" 6$$! )NT 3500,9 350%26)3)/. 0/2 0$2 6 $$ 06$ 2# (3 -(Z 2# (3 -(Z .234 6$$! 6$$! 6$$ 2# ,3 84!, /3# -(Z 0,, /3#).
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Functional overview STM32F050xx 3 Functional overview 3.1 ARM® CortexTM-M0 core with embedded Flash and SRAM The ARM Cortex™-M0 processor is the latest generation of ARM processors for embedded systems. It has been developed to provide a low-cost platform that meets the needs of MCU implementation, with a reduced pin count and low-power consumption, while delivering outstanding computational performance and an advanced system response to interrupts.
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STM32F050xx 3.4 Functional overview Cyclic redundancy check calculation unit (CRC) The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit data word and a CRC-32 (Ethernet) polynomial. Among other applications, CRC-based techniques are used to verify data transmission or storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of verifying the Flash memory integrity.
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Functional overview 3.5.3 STM32F050xx Voltage regulator The regulator has three operating modes: main (MR), low power (LPR) and power down. ● MR is used in normal operating mode (Run) ● LPR can be used in Stop mode where the power demand is reduced ● Power down is used in Standby mode: the regulator output is in high impedance: the kernel circuitry is powered down, inducing zero consumption (but the contents of the registers and SRAM are lost) This regulator is always enabled after reset.
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STM32F050xx 3.6 Functional overview Clocks and startup System clock selection is performed on startup, however the internal RC 8 MHz oscillator is selected as default CPU clock on reset. An external 4-32 MHz clock can be selected, in which case it is monitored for failure. If failure is detected, the system automatically switches back to the internal RC oscillator. A software interrupt is generated if enabled.
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Functional overview 3.7 STM32F050xx General-purpose inputs/outputs (GPIOs) Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the GPIO pins are shared with digital or analog alternate functions. The I/O configuration can be locked if needed following a specific sequence in order to avoid spurious writing to the I/Os registers. 3.
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STM32F050xx 3.10 Functional overview Analog to digital converter (ADC) The 12-bit analog to digital converter has up to 16 external and 3 internal (temperature sensor, voltage reference, VBAT voltage measurement) channels and performs conversions in single-shot or scan modes. In scan mode, automatic conversion is performed on a selected group of analog inputs. The ADC can be served by the DMA controller.
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Functional overview 3.11 STM32F050xx Timers and watchdogs The STM32F050xx family devices include up to six general-purpose timers, one basic timer and an advanced control timer. Table 5 compares the features of the advanced-control, general-purpose and basic timers. Table 5.
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STM32F050xx Functional overview TIM2, TIM3 STM32F050xx devices feature two synchronizable 4-channel general-purpose timers. TIM2 is based on a 32-bit auto-reload up/downcounter and a 16-bit prescaler. TIM3 is based on a 16-bit auto-reload up/downcounter and a 16-bit prescaler. They feature 4 independent channels each for input capture/output compare, PWM or one-pulse mode output. This gives up to 12 input captures/output compares/PWMs on the largest packages.
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Functional overview 3.11.5 STM32F050xx SysTick timer This timer is dedicated to real-time operating systems, but could also be used as a standard down counter. It features: 3.12 ● A 24-bit down counter ● Autoreload capability ● Maskable system interrupt generation when the counter reaches 0.
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STM32F050xx 3.13 Functional overview Inter-integrated circuit interface (I2C) The I2C interface (I2C1) can operate in multimaster or slave mode. It can support Standard mode (up to 100 kbit/s), Fast mode (up to 400 kbit/s) and Fast Mode Plus (up to 1 Mbit/s) with 20 mA output drive. It supports 7-bit and 10-bit addressing modes, multiple 7-bit slave addresses (2 addresses, 1 with configurable mask). It also includes programmable analog and digital noise filters. Table 6.
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Functional overview 3.15 STM32F050xx Serial peripheral interface (SPI)/Inter-integrated sound interfaces (I2S) The SPI (SPI1) is able to communicate up to 18 Mbits/s in slave and master modes in fullduplex and half-duplex communication modes. The 3-bit prescaler gives 8 master mode frequencies and the frame size is configurable from 4 bits to 16 bits.
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STM32F050xx Pinouts and pin description 6"!4 0# 0# /3# ?). 0# /3# ?/54 0& /3#?). 0& /3#?/54 .234 633! 6$$! 0! 0! 0! 0" 0! 0" 0" 0" 0" 0" "//4 ,1&0 0& 0& 0! 0! 0! 0! 0! 0! 0" 0" 0" 0" 6$$ 0" 633 0" 0" 0" 0" 0! 0! 0! 0! 0! 0! 0" LQFP48 48-pin package pinout 6$$ 633 Figure 3.
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Pinouts and pin description UFQFPN28 28-pin package pinout 0" 0" 0" 0" 0" 0! 0! Figure 5. STM32F050xx 0! 0! 0! 0! 6$$ 633 0" 0! 0" 0! 0! 0! 0! 0! "//4 0& /3#?). 0& /3#?/54 .234 6$$! 0! 0! -3 6 Figure 6. TSSOP20 20-pin package pinout "//4 0& /3#?). 0& /3#?/54 0! 0! 0! 0! 6$$ 633 0" 0! 0! 0! .
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STM32F050xx Pinouts and pin description Table 7. Legend/abbreviations used in the pinout table Name Pin name Pin type Abbreviation Definition Unless otherwise specified in brackets below the pin name, the pin function during and after reset is the same as the actual pin name S Supply pin I Input only pin I/O Input / output pin FT 5 V tolerant I/O FTf 5 V tolerant I/O, FM+ capable TTa 3.3 V tolerant I/O directly connected to ADC TC Standard 3.
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Pinouts and pin description Pin definitions UFQFPN32 UFQFPN28 TSSOP20 1 - - - Pin name (function after reset) Pin type LQFP48 Pin number VBAT S I/O structure Table 8.
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STM32F050xx Pin definitions (continued) 16 12 12 12 Pin name (function after reset) PA6 Pin type TSSOP20 UFQFPN28 UFQFPN32 LQFP48 Pin number I/O I/O structure Table 8.
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Pinouts and pin description Pin definitions (continued) Pin name (function after reset) Pin type TSSOP20 UFQFPN28 UFQFPN32 LQFP48 Pin number I/O structure Table 8.
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STM32F050xx Pin definitions (continued) Pin name (function after reset) Pin type TSSOP20 UFQFPN28 UFQFPN32 LQFP48 Pin number I/O structure Table 8.
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Pin name Alternate functions selected through GPIOA_AFR registers for port A AF0 PA0 PA1 EVENTOUT PA2 PA3 AF1 AF2 USART1_CKS(1) TIM2_CH1_ ETR USART1_TX(1) TIM2_CH2 USART1_RX(1) TIM2_CH3 USART1_CTS (1) AF3 AF4 Doc ID 023683 Rev 1 AF6 TIM16_CH1 EVENTOUT TIM17_CH1 EVENTOUT TIM2_CH4 PA4 SPI1_NSS, I2S1_WS PA5 SPI1_SCK, I2S1_CK PA6 SPI1_MISO, I2S1_MCK TIM3_CH1 TIM1_BKIN PA7 SPI1_MOSI, I2S1_SD TIM3_CH2 TIM1_CH1N PA8 MCO USART1_CK TIM1_CH1 USART1_TX TIM1_CH2 I2C1_SCL(1) I2C
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Alternate functions selected through GPIOB_AFR registers for port B Pin name AF0 AF1 AF2 PB0 EVENTOUT TIM3_CH3 TIM1_CH2N PB1 TIM14_CH1 TIM3_CH4 TIM1_CH3N PB3 SPI1_SCK, I2S1_CK EVENTOUT TIM2_CH2 PB4 SPI1_MISO, I2S1_MCK TIM3_CH1 EVENTOUT PB5 SPI1_MOSI, I2S1_SD TIM3_CH2 TIM16_BKIN PB6 USART1_TX I2C1_SCL TIM16_CH1N PB7 USART1_RX I2C1_SDA TIM17_CH1N I2C1_SCL TIM16_CH1 I2C1_SDA TIM17_CH1 AF3 STM32F050xx Table 10.
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Memory mapping 5 STM32F050xx Memory mapping Figure 7.
PAGE 33
STM32F050xx Memory mapping Table 11.
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Memory mapping STM32F050xx Table 11.
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STM32F050xx Electrical characteristics 6 Electrical characteristics 6.1 Parameter conditions Unless otherwise specified, all voltages are referenced to VSS. 6.1.1 Minimum and maximum values Unless otherwise specified, the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at TA = 25 °C and TA = TAmax (given by the selected temperature range).
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Electrical characteristics 6.1.6 STM32F050xx Power supply scheme Figure 10. Power supply scheme 6"!4 "ACKUP CIRCUITRY ,3% 24# 7AKE UP LOGIC "ACKUP REGISTERS /54 '0 ) /S ). ,EVEL SHIFTER 0O WER SWI TCH 6 )/ ,OGIC +ERNEL LOGIC #05 $IGITAL -EMORIES 6$$ § 6$$ § N& § & 6$$! 2EGULATOR § 633 6$$! 62%& 62%& N& & !$# $!# !NALOG 2#S 0,, 633! -3 6 Caution: Each power supply pair (VDD/VSS, VDDA/VSSA etc.
PAGE 37
STM32F050xx 6.2 Electrical characteristics Absolute maximum ratings Stresses above the absolute maximum ratings listed in Table 12: Voltage characteristics, Table 13: Current characteristics, and Table 14: Thermal characteristics may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Table 12.
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Electrical characteristics STM32F050xx 2. This current consumption must be correctly distributed over all I/Os and control pins. The total output current must not be sunk/sourced between two consecutive power supply pins referring to high pin count QFP packages. 3. Positive injection is not possible on these I/Os and does not occur for input voltages lower than the specified maximum value. 4. A positive injection is induced by VIN>VDD while a negative injection is induced by VIN
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STM32F050xx Electrical characteristics 6.3 Operating conditions 6.3.1 General operating conditions Table 15. General operating conditions Symbol Parameter Conditions Min Max fHCLK Internal AHB clock frequency 0 48 fPCLK Internal APB clock frequency 0 48 VDD Standard operating voltage 2 3.6 2 3.6 2.4 3.6 1.65 3.6 –0.3 VDD+0.3 –0.3 VDDA+0.3 –0.3 5.5 BOOT0 0 5.
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Electrical characteristics 6.3.2 STM32F050xx Operating conditions at power-up / power-down The parameters given in Table 16 are derived from tests performed under the ambient temperature condition summarized in Table 15. Table 16. Operating conditions at power-up / power-down Symbol Parameter tVDD tVDDA 6.3.
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STM32F050xx Electrical characteristics Table 18. Symbol Programmable voltage detector characteristics (continued) Parameter Min(1) Typ Max(1) Unit Rising edge 2.57 2.68 2.79 V Falling edge 2.47 2.58 2.69 V Rising edge 2.66 2.78 2.9 V Falling edge 2.56 2.68 2.8 V Rising edge 2.76 2.88 3 V Falling edge 2.66 2.78 2.
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Electrical characteristics 6.3.5 STM32F050xx Supply current characteristics The current consumption is a function of several parameters and factors such as the operating voltage, ambient temperature, I/O pin loading, device software configuration, operating frequencies, I/O pin switching rate, program location in memory and executed binary code. The current consumption is measured as described in Figure 11: Current consumption measurement scheme.
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STM32F050xx Table 20. Electrical characteristics Typical and maximum current consumption from VDD supply at VDD = 3.
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Electrical characteristics Table 21. STM32F050xx Typical and maximum current consumption from the VDDA supply VDDA = 2.4 V Symbol Parameter Conditions (1) VDDA = 3.
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STM32F050xx Table 22. Electrical characteristics Typical and maximum VDD consumption in Stop and Standby modes Symbol Parameter IDD Max(1) 2.0 V 2.4 V 2.7 V 3.0 V 3.3 V 3.6 V TA = TA = TA = 25 °C 85 °C 105 °C Conditions Regulator in run mode, all oscillators OFF Supply current in Regulator in low-power Stop mode mode, all oscillators OFF Supply current in Standby mode Typ @VDD (VDD = VDDA) 15 15.1 15.25 15.45 15.7 3.15 3.25 3.35 3.45 3.7 16 18(2) 38 55(2) 4 5.
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Electrical characteristics Table 24. STM32F050xx Typical and maximum current consumption from VBAT supply Max(1) Backup domain IDD_VBAT supply current = 3.6 V = 3.3 V = 2.7 V Conditions = 2.4 V Parameter = 1.8 V Symbol = 1.65 V Typ @ VBAT LSE & RTC ON; “Xtal mode”: lower driving 0.41 0.43 0.53 0.58 0.71 0.80 capability; LSEDRV[1:0] = '00' TA = 25 °C TA = 85 °C TA = 105 °C 0.85 1.1 1.5 Unit µA LSE & RTC ON; “Xtal mode” higher driving 0.71 0.75 0.85 0.91 1.06 1.
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STM32F050xx Table 25. Electrical characteristics Typical current consumption in Run mode, code with data processing running from Flash Typ Symbol IDD Parameter Conditions Supply current in Run mode from VDD supply Running from HSE crystal clock 8 MHz, code executing from Flash IDDA Supply current in Run mode from VDDA supply fHCLK Peripherals enabled Peripherals disabled 48 MHz 18.4 11.4 36 MHz 13.9 8.9 32 MHz 12.4 7.9 24 MHz 9.9 6.2 16 MHz 6.6 4.3 8 MHz 3.3 2.2 4 MHz 1.7 1.
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Electrical characteristics Table 26. STM32F050xx Typical current consumption in Sleep mode, code running from Flash or RAM Typ Symbol IDD Parameter Conditions Supply current in Sleep mode from VDD supply Running from HSE crystal clock 8 MHz, code executing from Flash or RAM IDDA 48/97 Supply current in Sleep mode from VDDA supply fHCLK Peripherals Peripherals enabled disabled 48 MHz 10.7 2.4 36 MHz 8.1 1.8 32 MHz 7.1 1.6 24 MHz 5.5 1.3 16 MHz 3.7 0.9 8 MHz 1.9 0.5 4 MHz 1.
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STM32F050xx Electrical characteristics I/O system current consumption The current consumption of the I/O system has two components: static and dynamic. I/O static current consumption All the I/Os used as inputs with pull-up generate current consumption when the pin is externally held low. The value of this current consumption can be simply computed by using the pull-up/pull-down resistors values given in Table 45: I/O static characteristics.
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Electrical characteristics Table 27. Symbol STM32F050xx Switching output I/O current consumption Parameter Conditions(1) VDD = 3.3 V C =CINT VDD = 3.3 V CEXT = 0 pF C = CINT + CEXT+ CS VDD = 3.3 V CEXT = 10 pF C = CINT + CEXT+ CS ISW I/O current consumption VDD = 3.3 V CEXT = 22 pF C = CINT + CEXT+ CS VDD = 3.3 V CEXT = 33 pF C = CINT + CEXT+ CS VDD = 3.3 V CEXT = 47 pF C = CINT + CEXT+ CS C = Cint VDD = 2.4 V CEXT = 47 pF C = CINT + CEXT+ CS C = Cint 1. CS = 7 pF (estimated value).
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STM32F050xx Electrical characteristics On-chip peripheral current consumption The current consumption of the on-chip peripherals is given in Table 28.
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Electrical characteristics 6.3.6 STM32F050xx External clock source characteristics High-speed external user clock generated from an external source In bypass mode the HSE oscillator is switched off and the input pin is a standard GPIO. The external clock signal has to respect the I/O characteristics in Section 6.3.13. However, the recommended clock input waveform is shown in Figure 12: High-speed external clock source AC timing diagram. Table 29.
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STM32F050xx Electrical characteristics Low-speed external user clock generated from an external source In bypass mode the LSE oscillator is switched off and the input pin is a standard GPIO. The external clock signal has to respect the I/O characteristics in Section 6.3.13. However, the recommended clock input waveform is shown in Figure 13. Table 30. Low-speed external user clock characteristics Parameter(1) Symbol Conditions Min Typ Max Unit - 32.
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Electrical characteristics STM32F050xx High-speed external clock generated from a crystal/ceramic resonator The high-speed external (HSE) clock can be supplied with a 4 to 32 MHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on design simulation results obtained with typical external components specified in Table 31.
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STM32F050xx Electrical characteristics Figure 14. Typical application with an 8 MHz crystal 2ESONATOR WITH INTEGRATED CAPACITORS #, F(3% /3#?). -( Z RESONATOR #, 2%84 2& "IAS CONTROLLED GAIN /3#?/5 4 -3 6 1. REXT value depends on the crystal characteristics. Low-speed external clock generated from a crystal resonator The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal resonator oscillator.
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Electrical characteristics STM32F050xx Figure 15. Typical application with a 32.768 kHz crystal 2ESONATOR WITH INTEGRATED CAPACITORS #, F,3% /3# ?). $RIVE PROGRAMMABLE AMPLIFIER K( Z RESONATOR #, /3# ?/5 4 -3 6 Note: 56/97 An external resistor is not required between OSC32_IN and OSC32_OUT and it is forbidden to add one.
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STM32F050xx 6.3.7 Electrical characteristics Internal clock source characteristics The parameters given in Table 33 are derived from tests performed under ambient temperature and supply voltage conditions summarized in Table 15: General operating conditions. The provided curves are characterization results, not tested in production. High-speed internal (HSI) RC oscillator Table 33.
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Electrical characteristics STM32F050xx High-speed internal 14 MHz (HSI14) RC oscillator (dedicated to ADC) Table 34. HSI14 oscillator characteristics(1) Symbol fHSI14 TRIM Parameter Conditions Frequency HSI14 user-trimming step Min Typ - 14 - DuCy(HSI14) Duty cycle 45 Accuracy of the HSI14 oscillator (factory calibrated) TA = –10 to 85 °C TA = 25 °C tsu(HSI14) IDDA(HSI14) HSI14 oscillator startup time HSI14 oscillator power consumption % 1 - 55 (2) % (3) - 5.1 % –3.2(3) - 3.
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STM32F050xx Electrical characteristics Low-speed internal (LSI) RC oscillator Table 35. LSI oscillator characteristics(1) Symbol fLSI Min Typ Max Unit 30 40 50 kHz LSI oscillator startup time - - 85 µs LSI oscillator power consumption - 0.75 1.2 µA Frequency tsu(LSI)(2) IDDA(LSI) Parameter (2) 1. VDDA = 3.3 V, TA = –40 to 105 °C unless otherwise specified. 2. Guaranteed by design, not tested in production.
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Electrical characteristics 6.3.8 STM32F050xx PLL characteristics The parameters given in Table 37 are derived from tests performed under ambient temperature and supply voltage conditions summarized in Table 15: General operating conditions. Table 37. PLL characteristics Value Symbol Parameter Unit Min Typ Max PLL input clock(1) 1(2) 8.
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STM32F050xx 6.3.9 Electrical characteristics Memory characteristics Flash memory The characteristics are given at TA = –40 to 105 °C unless otherwise specified. Table 38. Flash memory characteristics Min Typ Max(1) Unit 16-bit programming time TA = –40 to +105 °C 40 53.
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Electrical characteristics Table 40. STM32F050xx EMS characteristics Symbol Parameter Level/ Class Conditions VFESD VDD = 3.3 V, LQFP64, TA = +25 °C, Voltage limits to be applied on any I/O pin to fHCLK = 48 MHz induce a functional disturbance conforms to IEC 61000-4-2 2B VEFTB Fast transient voltage burst limits to be applied through 100 pF on VDD and VSS pins to induce a functional disturbance VDD = 3.
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STM32F050xx 6.3.11 Electrical characteristics Electrical sensitivity characteristics Based on three different tests (ESD, LU) using specific measurement methods, the device is stressed in order to determine its performance in terms of electrical sensitivity. Electrostatic discharge (ESD) Electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination.
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Electrical characteristics STM32F050xx The characterization results are given in Table 44. Table 44.
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STM32F050xx 6.3.13 Electrical characteristics I/O port characteristics General input/output characteristics Unless otherwise specified, the parameters given in Table 45 are derived from tests performed under the conditions summarized in Table 15: General operating conditions. All I/Os are CMOS and TTL compliant. Table 45. Symbol VIL I/O static characteristics Parameter Low level input voltage Conditions High level input voltage Vhys Ilkg RPU Weak pull-up equivalent resistor(3) Unit (1) - 0.
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Electrical characteristics Table 45. Symbol STM32F050xx I/O static characteristics (continued) Parameter RPD Weak pull-down equivalent resistor(3) CIO I/O pin capacitance Conditions Min Typ Max Unit VIN = VDD 25 40 55 kΩ - 5 - pF 1. Data based on design simulation only. Not tested in production. 2. Leakage could be higher than maximum value, if negative current is injected on adjacent pins. 3.
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STM32F050xx Electrical characteristics All I/Os are CMOS and TTL compliant (no software configuration required). Their characteristics cover more than the strict CMOS-technology or TTL parameters. The coverage of these requirements is shown in Figure 18 and Figure 19 for standard I/Os, and in Figure 20 and Figure 21 for 5 V tolerant I/Os. The following curves are design simulation results, not tested in production. Figure 18.
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Electrical characteristics STM32F050xx Figure 20. Five volt tolerant (FT and FTf) I/O input characteristics - CMOS port VIL/VIH (V) CMOS standard requirements VIH min= 0.7VDD 2.0 = 0.5 -0.2 75V DD Input range not guaranteed 1.0 0.2 V DD+ V IHmin = 0.4 V ILmax CMOS standard requirements VILmax = 0.3VDD 0.5 VDD (V) 2.0 3.6 MS30257V1 Figure 21. Five volt tolerant (FT and FTf) I/O input characteristics - TTL port VIL/VIH (V) TTL standard requirements VIHmin = 2 V 2.
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STM32F050xx Electrical characteristics Output driving current The GPIOs (general purpose input/outputs) can sink or source up to +/-8 mA, and sink or source up to +/- 20 mA (with a relaxed VOL/VOH). In the user application, the number of I/O pins which can drive current must be limited to respect the absolute maximum rating specified in Section 6.
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Electrical characteristics STM32F050xx Input/output AC characteristics The definition and values of input/output AC characteristics are given in Figure 22 and Table 47, respectively. Unless otherwise specified, the parameters given are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 15: General operating conditions. Table 47.
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STM32F050xx Electrical characteristics Figure 22. I/O AC characteristics definition 90% 10% 50% 50% 90% 10% EXT ERNAL OUTPUT ON 50pF tr(I O)out tr(I O)out T Maximum frequency is achieved if (tr + tf) £ 2/3)T and if the duty cycle is (45-55%) when loaded by 50pF ai14131 6.3.14 NRST pin characteristics The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up resistor, RPU (see Table 45: I/O static characteristics).
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Electrical characteristics 6.3.15 STM32F050xx 12-bit ADC characteristics Unless otherwise specified, the parameters given in Table 49 are preliminary values derived from tests performed under ambient temperature, fPCLK2 frequency and VDDA supply voltage conditions summarized in Table 15: General operating conditions. Note: It is recommended to perform a calibration after each power-up. Table 49.
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STM32F050xx Electrical characteristics Equation 1: RAIN max formula TS R AIN < --------------------------------------------------------------- – R ADC N+2 f ADC × C ADC × ln ( 2 ) The formula above (Equation 1) is used to determine the maximum external impedance allowed for an error below 1/4 of LSB. Here N = 12 (from 12-bit resolution). Table 50. RAIN max for fADC = 14 MHz(1) Ts (cycles) tS (µs) RAIN max (kΩ) 1.5 0.11 0.4 7.5 0.54 5.9 13.5 0.96 11.4 28.5 2.04 25.2 41.5 2.96 37.2 55.
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Electrical characteristics STM32F050xx 2. ADC Accuracy vs. Negative Injection Current: Injecting negative current on any of the standard (nonrobust) analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to standard analog pins which may potentially inject negative current.
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STM32F050xx 6.3.16 Electrical characteristics Temperature sensor characteristics Table 52. TS characteristics Symbol Parameter Min Typ Max Unit - ±1 ±2 °C Average slope 4.0 4.3 4.6 mV/°C V25 Voltage at 25 °C 1.34 1.43 1.52 V tSTART(1) Startup time 4 - 10 µs TS_temp(1)(2) ADC sampling time when reading the temperature 17.1 - - µs TL(1) VSENSE linearity with temperature Avg_Slope (1) 1. Guaranteed by design, not tested in production. 2.
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Electrical characteristics Table 54. STM32F050xx TIMx(1) characteristics (continued) Symbol Parameter tCOUNTER 16-bit counter clock period tMAX_COUNT Conditions fTIMxCLK = 48 MHz Maximum possible count with 32-bit counter fTIMxCLK = 48 MHz Min Max Unit 1 65536 tTIMxCLK 0.0208 1365 µs - 65536 × 65536 tTIMxCLK - 89.48 s 1. TIMx is used as a general term to refer to the TIM1, TIM2, TIM3, TIM6, TIM14, TIM15, TIM16 and TIM17 timers. Table 55.
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STM32F050xx 6.3.19 Electrical characteristics Communication interfaces I2C interface characteristics Unless otherwise specified, the parameters given in Table 57 are derived from tests performed under ambient temperature, fPCLK frequency and VDD supply voltage conditions summarized in Table 15: General operating conditions. The I2C interface meets the requirements of the standard I2C communication protocol with the following restrictions: the I/O pins SDA and SCL are mapped to are not “true” opendrain.
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Electrical characteristics Table 58. STM32F050xx I2C analog filter characteristics(1) Symbol tSP Parameter Min Max Unit 50 260 ns Pulse width of spikes that are suppressed by the analog filter 1. Guaranteed by design, not tested in production. Figure 26.
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STM32F050xx Table 59.
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Electrical characteristics STM32F050xx Figure 27. SPI timing diagram - slave mode and CPHA = 0 NSS input tc(SCK) th(NSS) SCK Input tSU(NSS) CPHA= 0 CPOL=0 tw(SCKH) tw(SCKL) CPHA= 0 CPOL=1 tv(SO) ta(SO) MISO OUT P UT tr(SCK) tf(SCK) th(SO) MS B O UT BI T6 OUT tdis(SO) LSB OUT tsu(SI) MOSI I NPUT B I T1 IN M SB IN LSB IN th(SI) ai14134c Figure 28.
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STM32F050xx Electrical characteristics Figure 29. SPI timing diagram - master mode(1) High NSS input SCK Output SCK Output tc(SCK) CPHA= 0 CPOL=0 CPHA= 0 CPOL=1 CPHA=1 CPOL=0 CPHA=1 CPOL=1 tsu(MI) MISO INP UT tw(SCKH) tw(SCKL) MS BIN tr(SCK) tf(SCK) BI T6 IN LSB IN th(MI) MOSI OUTUT M SB OUT tv(MO) B I T1 OUT LSB OUT th(MO) ai14136 1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD.
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Electrical characteristics STM32F050xx I2S characteristics Table 60. Symbol fCK 1/tc(CK) Parameter I2S clock frequency Conditions Master mode (data: 16 bits, Audio frequency = 48 kHz) Slave mode 2 I S clock rise time tr(CK) 2 I S clock fall time tf(CK) tw(CKH) (1) I2S clock high time Capacitive load CL = 15 pF Min Max 1.597 1.601 MHz 0 6.
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STM32F050xx Electrical characteristics Figure 30. I2S slave timing diagram (Philips protocol) CK Input tc(CK) CPOL = 0 CPOL = 1 tw(CKH) th(WS) tw(CKL) WS input tv(SD_ST) tsu(WS) SDtransmit LSB transmit(2) MSB transmit Bitn transmit tsu(SD_SR) LSB receive(2) SDreceive th(SD_ST) LSB transmit th(SD_SR) MSB receive Bitn receive LSB receive ai14881b 1. Measurement points are done at CMOS levels: 0.3 × VDD and 0.7 × VDD. 2. LSB transmit/receive of the previously transmitted byte.
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Package characteristics STM32F050xx 7 Package characteristics 7.1 Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark.
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STM32F050xx Package characteristics Figure 32. LQFP48 - 7 x 7 mm, 48-pin low-profile quad flat package outline D ccc C D1 D3 A A2 25 36 24 37 L1 b E3 E1 E 48 Pin 1 identification 13 1 L A1 K c 12 5B_ME 1. Drawing is not to scale. Table 61. LQFP48 – 7 x 7 mm, 48-pin low-profile quad flat package mechanical data inches(1) millimeters Symbol Min Typ A Max Min Typ 1.600 A1 0.050 A2 1.350 b 0.170 c 0.090 D 8.800 D1 6.800 D3 Max 0.0630 0.150 0.0020 1.400 1.450 0.
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Package characteristics STM32F050xx Figure 33. LQFP48 recommended footprint 0.50 1.20 9.70 0.30 25 36 37 24 0.20 7.30 5.80 7.30 48 13 12 1 1.20 5.80 9.70 ai14911b 1. Drawing is not to scale. 2. Dimensions are in millimeters.
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STM32F050xx Package characteristics Figure 34. UFQFPN32 - 5 x 5 mm, 32-lead ultra thin fine pitch quad flat no-lead package outline Seating plane C ddd C A A1 A3 D e 16 9 17 8 E b E2 24 1 L 32 Pin # 1 ID R = 0.30 D2 L Bottom view A0B8_ME 1. Drawing is not to scale. 2. All leads/pads should also be soldered to the PCB to improve the lead/pad solder joint life. 3. There is an exposed die pad on the underside of the UFQFPN package.
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Package characteristics STM32F050xx Figure 35. UFQFPN32 recommended footprint 1. Drawing is not to scale. 2. Dimensions are in millimeters.
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STM32F050xx Package characteristics Figure 36. UFQFPN28 - 4 x 4 mm, 28-lead ultra thin fine pitch quad flat no-lead package outline $ " $ ! 3EATING 0LANE #O X 0IN CORNER % % , , 0IN )$ $ETAIL : $ETAIL : E 4 2O 4YP ! ! 3EATING 0LANE B ! " ?-%?6 1. Drawing is not to scale. 2. Dimensions are in millimeters. 3. All leads/pads should also be soldered to the PCB to improve the lead/pad solder joint life. Table 63.
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Package characteristics STM32F050xx Figure 37. UFQFPN28 recommended footprint 1. Dimensions are in millimeters 2. All leads/pads should also be soldered to the PCB to improve the lead/pad solder joint life.
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STM32F050xx Package characteristics Figure 38. TSSOP20 - 20-pin thin shrink small outline $ C % % K AAA #0 , ! ! ! , B E 9!?-% 1. Drawing is not to scale. Table 64. TSSOP20 – 20-pin thin shrink small outline package mechanical data inches(1) millimeters Symbol Min Typ A Max Min Typ 1.2 A1 0.05 A2 0.8 b 0.0472 0.15 0.002 1.05 0.0315 0.19 0.3 0.0075 0.0118 c 0.09 0.2 0.0035 0.0079 D 6.4 6.5 6.6 0.252 0.2559 0.2598 E 6.2 6.4 6.6 0.2441 0.
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Package characteristics STM32F050xx Figure 39. TSSOP20 recommended footprint 1.
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STM32F050xx 7.2 Package characteristics Thermal characteristics The maximum chip junction temperature (TJmax) must never exceed the values given in Table 15: General operating conditions on page 39.
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Package characteristics STM32F050xx Example 1: High-performance application Assuming the following application conditions: Maximum ambient temperature TAmax = 80 °C (measured according to JESD51-2), IDDmax = 50 mA, VDD = 3.5 V, maximum 20 I/Os used at the same time in output at low level with IOL = 8 mA, VOL= 0.4 V and maximum 8 I/Os used at the same time in output at low level with IOL = 20 mA, VOL= 1.3 V PINTmax = 50 mA × 3.5 V= 175 mW PIOmax = 20 × 8 mA × 0.4 V + 8 × 20 mA × 1.
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STM32F050xx 8 Part numbering Part numbering For a list of available options (memory, package, and so on) or for further information on any aspect of this device, please contact your nearest ST sales office.
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Revision history 9 STM32F050xx Revision history Table 66.
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STM32F050xx Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale.