Datasheet
Electrical characteristics STM8AF52/62xx, STM8AF51/61xx
80/110 Doc ID 14395 Rev 9
Figure 41. SPI timing diagram - master mode
1. Measurement points are at CMOS levels: 0.3 V
DD
and 0.7 V
DD
.
AI
3#+OUTPUT
#0(!
-/3)
/5454
-)3/
).0 54
#0(!
-3").
- 3"/54
")4).
,3"/54
,3").
#0/,
#0/,
" )4/54
.33INPUT
T
C3#+
T
W3#+(
T
W3#+,
T
R3#+
T
F3#+
T
H-)
(IGH
3#+OUTPUT
#0(!
#0(!
#0/,
#0/,
T
SU-)
T
V-/
T
H-/