User's Manual

User’s Guide – SDC-MSD40NBT
14
SDC-MSD40NBT_UsersGuide
© 2011 – 2012 Summit Data Communications, Inc. All rights reserved.
Short Frame Sync, Slave Mode
Figure 4: Short Frame Sync, Slave Mode
Reference
Description
Min.
Typ.
Max.
Unit
1
PCM bit clock frequency
128
-
2048
kHz
2
PCM bit clock high time
209
-
-
ns
3
PCM bit clock low time
209
-
-
ns
4
Setup time for BT_PCM_SYNC
before falling edge of BT_PCM_BCLK
50
-
-
ns
5
Hold time for BT_PCM_SYNC after
falling edge of BT_PCM_CLK
10
-
-
ns
6
Hold time of BT_PCM_OUT after
BT_PCM_CLK falling time
-
-
175
ns
7
Setup time for BT_PCM_IN before
BT_PCM_CLK falling edge
50
-
-
ns
8
Hold time for BT_PCM_IN after
BT_PCM_CLK falling edge
10
-
-
ns
9
Delay from falling edge of
BT_PCM_CLK during last bit period
to BT_PCM_OUT becoming high
impedance
-
-
100
ns
Table 6: Short Frame Sync, Slave Mode