User's Manual

User’s Guide – SDC-MSD40NBT
15
SDC-MSD40NBT_UsersGuide
© 2011 – 2012 Summit Data Communications, Inc. All rights reserved.
Long Frame Sync, Master Mode
Figure 5: Long Frame Sync, Master Mode
Reference
Description
Min.
Typ.
Max.
Unit
1
PCM bit clock frequency
128
-
2048
kHz
2
PCM bit clock high time
209
-
-
ns
3
PCM bit clock low time
209
-
-
ns
4
Delay from BT_PCM_CLK rising edge
to BT_PCM_SYNC high during first
bit time
-
-
50
ns
5
Delay from BT_PCM_CLK rising edge
to BT_PCM_SYNC low during third bit
time
-
-
50
ns
6
Delay from BT_PCM_CLK rising edge
to data valid on BT_PCM_OUT
-
-
50
ns
7
Setup time for BT_PCM_IN before
BT_PCM_CLK falling edge
50
-
-
ns
8
Hold time for BT_PCM_IN after
BT_PCM_CLK falling edge
10
-
-
ns
9
Delay from falling edge of
BT_PCM_CLK during last bit period
to BT_PCM_OUT becoming high
impedance
-
-
50
ns
Table 7: Long Frame Sync, Master Mode