User's Manual

User’s Guide – SDC-MSD40NBT
20
SDC-MSD40NBT_UsersGuide
© 2011 – 2012 Summit Data Communications, Inc. All rights reserved.
Pin
Number
Pin
Name
I/O
Voltage
Reference
Description
44
No Connect
Not Used. Leave Open (Float)
45
No Connect
Not Used. Leave Open (Float)
46
No Connect
Not Used. Leave Open (Float)
47
No Connect
Not Used. Leave Open (Float)
48
CHIP_PWD_L
I
VDDIO
Powers down both the BT and WLAN
radios, active low (see Note).
49
No Connect
Not Used. Leave Open (Float)
50
RSVD
I/O
VDDIO
Reserved for GPIO
51
No Connect
Not Used. Leave Open (Float)
52
RSVD
I/O
VDDIO
Reserved for GPIO
53
RSVD
I/O
VDDIO
Reserved for GPIO
54
RSVD
I/O
VDDIO
Reserved for GPIO
55
SDIO_CMD
I/O
VDDIO
SDIO Command
Note: See
“Integration
Considerations” for
additional
integration
information.
56
SDIO_CLK
I
VDDIO
SDIO Clock (25MHz
max)
57
SDIO_DATA_0
I/O
VDDIO
SDIO Data 0
58
SDIO_DATA_3
I/O
VDDIO
SDIO Data 3
59
SDIO_DATA_1
I/O
VDDIO
SDIO Data 1
60
GND
-
Ground
Table 9: Pin Definitions
Note Regarding SYS_RST_L and CHIP_PWD_L:
Simply releasing SYS_RST_L and CHIP_PWD_L does not guarantee that the BCM4329 chip in
the SSD40NBT module comes out of reset. Ensure that both VDD and VDDIO have been applied
to the SSD40NBT for at least 110 ms before attempting to initiate SDIO communications. A
slightly longer delay is better (safer).