Server User Manual
Table Of Contents
- Sun Netra™ CP3250 Blade Server User’s Guide
- Contents
- Figures
- Tables
- Preface
- Overview
- Hardware Installation and Service
- 2.1 Safety and Tool Requirements
- 2.2 Installing the Blade Server
- 2.3 Service Procedures
- 2.3.1 Hot-Swapping the Netra CP3250 Blade Server
- 2.3.2 Powering Off the Netra CP3250 Blade Server
- 2.3.3 Removing the Netra CP3250 Blade Server
- 2.3.4 Powering On the System
- 2.3.5 Automatic Power-Off Events
- 2.3.6 Servicing DIMMs
- 2.3.7 Installing the Optional Compact Flash Card
- 2.3.8 Installing Optional AMC
- 2.3.9 Adding or Replacing the Battery
- 2.3.10 Changing Jumper Settings
- 2.3.11 Checking DIP Switch Settings
- 2.3.12 Resetting the Netra CP3250 Blade Server
- Hardware Architecture
- Software Configuration
- Configuring and Using BIOS Firmware
- 5.1 About BIOS Settings
- 5.2 Changing the Configuration of a BIOS Menu Item
- 5.3 Setting the Boot Device Using BIOS Setup Screens
- 5.4 Setting Supervisor and User Passwords
- 5.5 Resetting the System Time and System Date
- 5.6 Updating the BIOS
- 5.7 Secondary BIOS Image
- 5.8 Perform a Live Firmware Upgrade
- 5.9 Power-On Self-Test
- 5.10 Changing POST Options
- BIOS Screens
- Physical Characteristics
- ShMM CLI and Commands
- Index
3-6 Sun Netra CP3250 Blade Server User’s Guide • April 2009
3.5.3 LPC Bus Interface
The LPC bus is a multiplexed (command, address, and data) serialized 4-bit bus
with optional side band signals. It replaces the ISA/X-bus and reduces pin count
(approximately 40) over the ISA/X-bus.
LPC is designed to reduce the cost of traditional X-bus devices and meet the data
transfer rate of X-bus, exceeding those data rates where appropriated. It performs
the same cycle types as the X-bus: Memory, I/O, DMA and Bus Master. And, it
increases the memory space from 16 Mbytes on the X-bus to 4 GB to allow BIOS
sizes much greater than 1 Mbyte and other memory devices outside of the
traditional 16 MByte range.
The LPC is software transparent and does not require special drivers or
configuration for its interface. The motherboard BIOS configures all devices at boot
up. It has the ability to support a variable number of wait states, to have I/O and
memory cycles retried in SMM handler and to support wake-up and other power
state transitions. The design meets LPC 1.0 design guidelines.
The LPC bus provides system connectivity to the following devices:
■ Redundant BIOS
■ TPM
■ IPMC
■ RS-232 Serial Ports
3.5.4 Redundant BIOS
The Sun Netra CP3250 blade server provides redundant 1-Mbyte BIOS chips that
support redundant BIOS images for increased reliability.
The redundant Flash PROMs and SRAM devices are used by the BIOS. Each PROM
is an 8 MB flash device. The primary flash device (FWH0) contains the primary BIOS
image, factory default settings, and user configured settings. The primary BIOS chip
is automatically selected for update during a firmware upgrade.
The secondary flash device (FWH1) contains a backup copy, normally of the last
known good BIOS image, factory default settings, and last good user-configured
settings. The secondary BIOS chip retains the original BIOS image, and can be used
through manual configuration if the primary BIOS is corrupt.
In the event of a checksum or other failure during boot of the primary BIOS image,
the H8 switches the system over to the secondary device to allow system boot
recovery.