Product Specs
Table Of Contents
- BMS002 BT5.2 LE Audio Module
- RF/Analog
- • Frequency spectrum: 2.402 GHz to 2.480 GHz
- • Receive sensitivity: -95 dBm (2 Mbps EDR)
- • Output Power：8±2dBm (BDR) , 6±2dBm (EDR)
- 4±2dBm (BLE1M/2M)
- Audio Codec
- • SBC,AAC, LDAC
- • 24-bit digital-to-analog converter (DAC) with 10
- • 24-bit analog-to-digital converter (ADC) with 95
- • Supports up to 24-bit, 192 kHz I2S digital audio
- 1.DEVICE OVERVIEW
- 3.Power-on/off sequence
- 4. Battery charge specification revision 1.2 (BC1.2)
- 6.Module Description
- 8. Electrical Characteristics
- 9.Recommended Reflow Temperature Profile:
- 10.QR code label information:
- 11.Certification
- 12.Standard Packing Information
- 13.Document History
Product Specification
Spec-BMS002-V1.7 Page
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2.4 Digital controller for class-G amplifier
The Class-G amplifier is used for power saving of playback, and it can adjust the HP amplifier power rail
according the audio content. The Class-G digital controller detects audio signal amplify and sends a control signal to
buck converter through GPIO. When source swing goes high, the digital controller makes the Class-G amplifier change
the DAC output from low-voltage to high-voltage state to avoid signal clipping. When source swing goes low, it has a
configurable hold time control to prevent the Class-G amplifier from frequently adjusting the voltage. If the signal stays
in a low state after a specific hold time, the digital controller sends a request to make the Class-G amplifier change the
output from a high-voltage state to a low-voltage state. Otherwise, the output stays in a high-voltage state.
Figure 2.4-1 shows the block diagram of the Class-G digital controller. The audio digital Class-G path includes
the following blocks: Preview FIFO, Frame Preview, EN-FSM, Hold Time control and DA signal generator. The EN-
FSM module enables each voltage level in Class G. The Class-G input source is from the O_08 and O_09 (the same as
downlink), which is defined in the audio interconnection. The output of DA Generator is sent to the analog DAC.
The Class-G digital controller supports the following features:
Support for the independent selection for Class-G amplifier high-voltage and low-voltage levels.
Support for programmable high-voltage and low-voltage thresholds in the digital controller.
Support for a programmable hold time in the digital controller to prevent frequently voltage switching.
Built-in signal generator hardware for the DA signal request to the Class-G amplifier.
3. Power-on/off sequence
PMIC manages the power-on and power-off of the handset. If the battery voltage is neither in the UVLO state nor
in the thermal condition, there are three methods to power on the handset system.
3.1 Pulling PWRKEY low (User presses PWRKEY.)
Pushing PWRKEY (pulling the PWRKEY pin to low level)
Pulling PWRKEY low is a typical method to turn on the handset. The system reset ends at the moment when all
default-on regulators are sequentially turned on. After that, the MCU will send the PWRHOLD signal back to PMIC for
acknowledgement. To successfully power on the handset, PWRKEY should be kept low until PMIC receives
PWRHOLD from the MCU.( shown in Figure 3.3-1)
3.2 Valid charger plug-in
Valid charger plug-in (CHRIN voltage within valid range)
The charger plug-in will also turn on the handset if the charger is valid and VSYS > UVLO, the handset will also
be powered on.( shown in Figure 3.2-1)
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