Data Sheet

;Sample routines for PIC18CXXX interface
/***********************************************************************************************************************/
;Initialize PIC18Cxxx portc in LS7366 compatible SPI
;Setup: master mode, SCK idle low, SDI/SDO datashift on high to low transition of SCK
;SS/ assertion/deassertion made with direct manipulation of RA5
;Initialize portc
CLRF PORTC ;Clear portc
CLRF LATC ;Clear data latches
MOVLW 0x10 ;RC4 is input, RC3 & RC5 are outputs
MOVWF TRISC ;RC3=CLK, RC4=SDI, RC5=SDO
BCF TRISA, 5 ;RA5=output
BSF PORTA, 5 ;RA5=SS/=high
CLRF SSPSTAT ;SMP=0 => SDI data sampled at mid-data
BSF SSPSTAT, CKE ;CKE=1 => data shifts on active to idle SCK transitions
MOVLW 0x21 ;SPI mode initialization data
MOVWF SSPCON ;Master mode, CLK/16, CKP=0 => CLK idles low
;data shifted on active to idle CLK edge
/***********************************************************************************************************************/
; WR_MDR0
BSF PORTA, 5 ;SS/=high
BCF PORTA, 5 ;SS/=low
MOVLW 0x88 ;LS7366 WR_MDR0 command
MOVWF SSPBUF ;Transmit command byte
LOOP1 BTFSS SSPSTAT, BF ;Transmission complete with BF flag set?
BRA LOOP1 ;No, check again
MOVF SSPBUF, W ;Dummy read to clear BF flag.
MOVLW 0xA3 ;MDR0 data:fck/2, synchronous index. index=rcntr, x4
MOVWF SSPBUF ;Transmit data
LOOP2 BTFSS SSPSTAT, BF ;BF set?
BRA LOOP2 ;No, check again
BSF PORTA, 5 ;SS/=high
/***********************************************************************************************************************/
;RD_MDR0
BSF PORTA, 5 ;SS/=high
BCF PORTA, 5 ;SS/=low
MOVLW 0x48 ;LS7366 RD_MDR0 command
MOVWF SSPBUF ;Transmit command byte
LOOP1 BTFSS SSPSTAT, BF ;BF flag set?
BRA LOOP1 ;No, check again
MOVWF SSPBUF ;Send dummy byte to generate clock & receive data
LOOP2 BTFSS SSPSTAT, BF ;BF flag set?
BRA LOOP2 ;No, check again
MOVF SSPBUF, W ;Recieved data in WREG.
MOVWF RXDATA ;Save received data in RAM
BSF PORTA, 5 ;SS/=high
7366R-041906-13