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Low Voltage Intel

Xeon™ Processor

with 800 MHz System Bus

Datasheet

Product Features

The Low Voltage Intel

Xeon™ processor with 800 MHz system bus is designed for

high-performance dual-processor applications. Based on the Intel NetBurst

microarchitecture

and the Hyper-Threading Technology, it is binary compatible with previous Intel

Architecture

(IA-32) processors. The Low Voltage Intel Xeon processor with 800 MHz system bus is scalable

to two processors in a multiprocessor system providing exceptional performance for applications

running on advanced operating systems such as Windows XP*, Windows Server* 2003, Linux*,

and UNIX*.

■ Available at 2.80 GHz

■ 90 nm process technology

■ Dual processing support

■ Binary compatible with applications

running on previous members of Intel’s

IA-32 microprocessor line

■ Intel NetBurst

microarchitecture

■ Hyper-Threading Technology

■ Supports Execute Disable Bit capability

■ Hardware support for multithreaded

applications

■ Faster 800 MHz system bus

■ Rapid Execution Engine: Arithmetic Logic

Units (ALUs) run at twice the processor

core frequency

■ Hyper-Pipelined Technology

■ Advanced Dynamic Execution

■ Very deep out-of-order execution

■ Enhanced branch prediction

■ Includes 16-KB Level 1 data cache

■ Intel

Extended Memory 64 Technology

■ 1-MB Advanced Transfer Cache (On-die,

full speed Level 2 (L2) Cache) with 8-way

associativity and Error Correcting Code

(ECC)

■ Enables system support of up to 64 GB of

physical memory

■ 144 Streaming SIMD Extensions 2 (SSE2)

instructions

■ 13 Streaming SIMD Extensions 3 (SSE3)

instructions

■ Enhanced floating-point and multimedia

unit for enhanced video, audio, encryption,

and 3D performance

■ System Management mode

■ Thermal Monitor

■ Machine Check Architecture (MCA)

Document Number: 304097-001US

October 2004

The Low Voltage Intel Xeon processor with 800 MHz

system bus delivers compute power at unparalleled value

and flexibility for powerful workstations, internet

infrastructure, and departmental server applications. The

Intel NetBurst

microarchitecture and Hyper-Threading

Technology deliver outstanding performance and

headroom for peak internet server workloads, resulting in

faster response times, support for more users, and

improved scalability.

Summary of content (86 pages)

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Low Voltage Intel® Xeon™ Processor with 800 MHz System Bus Datasheet Product Features ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Available at 2.
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INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT.
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Contents 1.0 Introduction....................................................................................................................................9 1.1 1.2 1.3 2.0 Electrical Specifications ............................................................................................................. 13 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 2.10 2.11 3.0 Signal Definitions ................................................................................................................
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6.2 7.0 Features........................................................................................................................................ 79 7.1 7.2 8.0 Power-On Configuration Options........................................................................................ 79 Clock Control and Low Power States ................................................................................. 79 7.2.1 Normal State................................................................................
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Figures 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Phase Lock Loop (PLL) Filter Requirements ............................................................................. 15 Low Voltage Intel® Xeon™ Processor with 800 MHz System Bus Load Current vs. Time (VRM 10.0) ........................................................................................................................ 27 VCC Static and Transient Tolerance ..........................................................................................
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Tables 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 6 Features of the Low Voltage Intel® Xeon™ Processor with 800 MHz System Bus ..................... 9 Core Frequency to Front Side Bus Multiplier Configuration ....................................................... 14 BSEL[1:0] Frequency Table ....................................................................................................... 15 Voltage Identification Definition ..............................................
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Revision History Datasheet Date Revision October 2004 001 Description Initial release 7
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1.0 Introduction The Low Voltage Intel® Xeon™ processor with 800 MHz system bus is a 32-bit processor based on improvements to the Intel NetBurst® microarchitecture. It maintains the tradition of compatibility with IA-32 software and includes features found in the Low-Voltage Intel® Xeon™ processor such as Hyper-Pipelined Technology, a Rapid Execution Engine, and an Execution Trace Cache.
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Platforms based on the Low Voltage Intel® Xeon™ processor with 800 MHz system bus implement independent power planes for each system bus agent. As a result, the processor core voltage (V CC) and system bus termination voltage (VTT) must connect to separate supplies. The processor core voltage uses power delivery guidelines denoted by VRM 10.0 and the associated load line (see Voltage Regulator Module (VRM) and Enterprise Voltage Regulator-Down (EVRD) 10.0 Design Guidelines for further details).
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• Enterprise Voltage Regulator Down (EVRD) — DC-DC converter integrated onto the system board that provide the correct voltage and current for the processor based on the logic state of the VID bits. • Flip Chip Micro Pin Grid Array (FC-mPGA4) Package — The processor package is a Flip Chip Micro Pin Grid Array (FC-mPGA4), consisting of a processor core mounted on a pinned substrate with an integrated heat spreader (IHS). This package technology employs a 1.27 mm [0.05 in.] pitch for the processor pins.
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1.
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2.0 Electrical Specifications 2.1 Power and Ground Pins For clean on-chip power distribution, the processor has 181 VCC (power) and 185 V SS (ground) inputs. All VCC pins must be connected to the processor power plane, while all VSS pins must be connected to the system ground plane. The processor VCC pins must be supplied with the voltage determined by the processor Voltage IDentification (VID) pins.
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2.2.3 Front Side Bus AGTL+ Decoupling The Low Voltage Intel® Xeon™ processor with 800 MHz system bus integrates signal termination on the die, as well as part of the required high frequency decoupling capacitance on the processor package. However, additional high frequency capacitance must be added to the baseboard to properly decouple the return currents from the front side bus. Bulk decoupling must also be provided by the baseboard for proper AGTL+ bus operation. 2.
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Table 3. 2.3.2 BSEL[1:0] Frequency Table BSEL1 BSEL0 Bus Clock Frequency 0 0 Reserved 0 1 Reserved 1 0 200 MHz 1 1 Reserved Phase Lock Loop (PLL) and Filter VCCA and VCCIOPLL are power sources required by the PLL clock generators on the Low Voltage Intel® Xeon™ processor with 800 MHz system bus. Since these PLLs are analog in nature, they require quiet power supplies for minimum jitter.
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2.4 Voltage Identification (VID) The Voltage Identification (VID) specification for the Low Voltage Intel® Xeon™ processor with 800 MHz system bus is defined by the Voltage Regulator Module (VRM) and Enterprise Voltage Regulator-Down (EVRD) 10.0 Design Guidelines. The voltage set by the VID signals is the maximum voltage allowed by the processor (please see Section 2.11.1 for VCC overshoot specifications). VID signals are open drain outputs, which must be pulled up to VTT.
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Table 4. Voltage Identification Definition VID5 VID4 VID3 VID2 VID1 VID0 VCC_MAX VID5 VID4 VID3 VID2 VID1 VID0 VCC_MAX 0 0 1 0 1 0 0.8375 0 1 1 0 1 0 1.2125 1 0 1 0 0 1 0.8500 1 1 1 0 0 1 1.2250 0 0 1 0 0 1 0.8625 0 1 1 0 0 1 1.2375 1 0 1 0 0 0 0.8750 1 1 1 0 0 0 1.2500 0 0 1 0 0 0 0.8875 0 1 1 0 0 0 1.2625 1 0 0 1 1 1 0.9000 1 1 0 1 1 1 1.2750 0 0 0 1 1 1 0.9125 0 1 0 1 1 1 1.
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2.5 Reserved or Unused Pins All Reserved pins must remain unconnected. Connection of these pins to VCC, VTT, VSS, or to any other signal (including each other) can result in component malfunction or incompatibility with future processors. See Section 5.0 for a pin listing of the processor and the location of all Reserved pins. For reliable operation, always connect unused inputs or bidirectional signals to an appropriate signal level.
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2.6 Front Side Bus Signal Groups The front side bus signals have been combined into groups by buffer type. AGTL+ input signals have differential input buffers, which use GTLREF as a reference level. In this document, the term “AGTL+ Input” refers to the AGTL+ input group as well as the AGTL+ I/O group when receiving. Similarly, “AGTL+ Output” refers to the AGTL+ output group as well as the AGTL+ I/O group when driving.
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Table 5. Front Side Bus Signal Groups Type Signals1 AGTL+ Common Clock Input Synchronous to BCLK[1:0] BPRI#, BR[3:1]#2,3, DEFER#, RESET#, RS[2:0]#, RSP#, TRDY# AGTL+ Common Clock I/O Synchronous to BCLK[1:0] ADS#, AP[1:0]#, BINIT#4, BNR#4, BPM[5:0]#, BR0#2,3, DBSY#, DP[3:0]#, DRDY#, HIT#4, HITM#4, LOCK#, MCERR#4 AGTL+ Source Synchronous I/O Synchronous to assoc.
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Table 6 outlines the signals which include on-die termination (RTT) and lists signals which include additional on-die resistance (RL). Open drain signals are also included. Table 7 provides signal reference voltages Table 6.
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2.7 GTL+ Asynchronous and AGTL+ Asynchronous Signals The Low Voltage Intel® Xeon™ processor with 800 MHz system bus does not use CMOS voltage levels on any signals that connect to the processor silicon. As a result, input signals such as A20M#, FORCEPR#, IGNNE#, INIT#, LINT0/INTR, LINT1/NMI, SMI#, SLP#, and STPCLK# use GTL input buffers. Legacy output THERMTRIP# uses a GTL+ output buffers.
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2.10 Absolute Maximum and Minimum Ratings Table 8 specifies absolute maximum and minimum ratings. Within functional operation limits, functionality and long-term reliability can be expected. At conditions outside functional operation condition limits, but within absolute maximum and minimum ratings, neither functionality nor long term reliability can be expected.
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2.11 Processor DC Specifications The processor DC specifications in this section are defined at the processor core (pads) unless noted otherwise. See Section 5.1 for the Low Voltage Intel® Xeon™ processor with 800 MHz system bus pin listings and Section 4.1 for signal definitions. Voltage and current specifications are detailed in Table 9. For platform power delivery planning refer to Table 10, which provides VCC static and transient tolerances. This same information is presented graphically in Figure 3.
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Table 9. Symbol Voltage and Current Specifications Parameter Min. Typ. Max. Unit Notes1 1.2000 V 2, 3 VID - ICC (max) * 1.25 mΩ V 3, 4, 5, 6 VID range VID range for Low Voltage Intel® Xeon™ processor with 800 MHz system bus 1.1125 VCC VCC for Low Voltage Intel® Xeon™ processor with 800 MHz system bus See Table 10 and Figure 3 VTT Front Side Bus termination voltage (DC specification) 1.176 1.20 1.224 V 7 Front Side Bus termination voltage (AC & DC specification) 1.140 1.20 1.
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11. These specifications apply to the PLL power pins VCCA, VCCIOPLL, and VSSA. See Section 2.3.2 for details. These parameters are based on design characterization and are not tested. 12.This specification represents a total current for all GTLREF pins. 13.The current specified is also for HALT State. 14.The maximum instantaneous current the processor will draw while the thermal control circuit is active as indicated by the assertion of the PROCHOT# signal is the maximum ICC for the processor. 15.
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Figure 2. Low Voltage Intel® Xeon™ Processor with 800 MHz System Bus Load Current vs. Time (VRM 10.0) VRM 10LV Current 62 Sustained Current (A) 61 60 59 58 57 56 55 0.01 0.1 1 10 100 1000 Time Duration (s) NOTES: 1. Processor or voltage regulator thermal protection circuitry should not trip for load currents greater than ICC_TDC. 2. Not 100% tested. Specified by design characterization.
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Table 10. VCC Static and Transient Tolerance Voltage Deviation from VID Setting (V)1,2,3 ICC VCC_Max VCC_Typ VCC_Min 0 VID - 0.000 VID - 0.020 VID - 0.040 5 VID - 0.006 VID - 0.026 VID - 0.046 10 VID - 0.013 VID - 0.033 VID - 0.052 15 VID - 0.019 VID - 0.039 VID - 0.059 20 VID - 0.025 VID - 0.045 VID - 0.065 25 VID - 0.031 VID - 0.051 VID - 0.071 30 VID - 0.038 VID - 0.058 VID - 0.077 35 VID - 0.044 VID - 0.064 VID - 0.084 40 VID - 0.050 VID - 0.070 VID - 0.
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Figure 3. VCC Static and Transient Tolerance Icc [A] 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 95 100 105 110 115 120 VID - 0.000 VID - 0.020 VCC Maximum VID - 0.040 VID - 0.060 Vcc [V] VID - 0.080 VID - 0.100 VID - 0.120 VID - 0.140 VCC Typical V CC Minimum VID - 0.160 VID - 0.180 VID - 0.200 NOTES: 1. The VCC_MIN and VCC_MAX loadlines represent static and transient limits. Please see Section 2.11.1 for VCC overshoot specifications. 2.
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2.11.1 VCC Overshoot Specification The Low Voltage Intel® Xeon™ processor with 800 MHz system bus can tolerate short transient overshoot events where VCC exceeds the VID voltage when transitioning from a high-to-low current load condition. This overshoot cannot exceed VID + VOS_MAX. (VOS_MAX is the maximum allowable overshoot above VID). These specifications apply to the processor die voltage as measured across the VCCSENSE and VSSSENSE pins. Table 11. VCC Overshoot Specifications Symbol Figure 4.
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2.11.2 Die Voltage Validation Overshoot events from application testing on processor must meet the specifications in Table 11 when measured across the VCCSENSE and VSSSENSE pins. Overshoot events that are < 10 ns in duration may be ignored. These measurement of processor die level overshoot should be taken with a 100 MHz bandwidth limited oscilloscope. Table 12. BSEL[1:0] and VID[5:0] Signal Group DC Specifications Symbol Parameter Min. Typ.
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Table 14. PWRGOOD Input and TAP Signal Group DC Specifications Symbol Parameter Notes Min. Max. Unit 200 350 mV 3 1,2 VHYS Input Hysteresis Vt+ Input Low to High Threshold Voltage 0.5 * (VTT + VHYS_MIN ) 0.5 * (VTT + VHYS_MAX) V 4 Vt- Input High to Low Threshold Voltage 0.5 * (VTT - VHYS_MAX) 0.
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Table 16. VIDPWRGD DC Specifications Symbol Datasheet Parameter Min. Max. Unit VIL Input Low Voltage 0.0 0.30 V VIH Input High Voltage 0.
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3.0 Mechanical Specifications The Low Voltage Intel® Xeon™ processor with 800 MHz system bus is packaged in Flip Chip Micro Pin Grid Array (FC-mPGA4) package that interfaces to the baseboard via an mPGA604 socket. The package consists of a processor core mounted on a substrate pin-carrier. An integrated heat spreader (IHS) is attached to the package substrate and core and serves as the mating surface for processor component thermal solutions, such as a heat sink.
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Figure 6.
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Figure 7.
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3.2 Processor Component Keepout Zones The processor may contain components on the substrate that define component keepout zone requirements. A thermal and mechanical solution design must not intrude into the required keepout zones. Decoupling capacitors are typically mounted to either the topside or pin-side of the package substrate. See Figure 7 for keepout zones. 3.3 Package Loading Specifications Table 17 provides dynamic and static load specifications for the processor package.
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3.4 Package Handling Guidelines Table 18 includes a list of guidelines on a package handling in terms of recommended maximum loading on the processor IHS relative to a fixed substrate. These package handling loads may be experienced during heat sink removal. Table 18. Package Handling Guidelines Parameter Maximum Recommended Notes Shear 356 N 80 lbf 1, 4, 5 Tensile 156 N 35 lbf 2, 4, 5 Torque 8 N-m 70 lbf-in 3, 4, 5 NOTES: 1.
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3.8 Processor Markings Figure 8 shows the topside markings and Figure 9 shows the bottom-side markings on the processor. These diagrams are to aid in the identification of the Low Voltage Intel® Xeon™ processor with 800 MHz system bus. Figure 8. Processor Top-Side Markings (Example) Processor Name i(m) ©’03 2D Matrix Includes ATPO and Serial Number (front end mark) ATPO Serial Number Pin 1 Indicator NOTES: 1. All characters will be in upper case. 2. Drawing is not to scale. Figure 9.
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3.9 Processor Pinout Coordinates Figure 10 and Figure 11 show the top and bottom view of the processor pin coordinates, respectively. The coordinates are referred to throughout the document to identify processor pins. Figure 10.
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Figure 11.
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4.0 Signal Definitions 4.1 Signal Definitions Table 20. Signal Definitions (Sheet 1 of 9) Name A[35:3]# Type Description Notes I/O A[35:3]# (Address) define a 236-byte physical memory address space. In sub-phase 1 of the address phase, these pins transmit the address of a transaction. In sub-phase 2, these pins transmit transaction type information. These signals must connect the appropriate pins of all agents on the front side bus. A[35:3]# are protected by parity signals AP[1:0]#.
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Table 20. Name BINIT# Signal Definitions (Sheet 2 of 9) Type I/O Description BINIT# (Bus Initialization) may be observed and driven by all processor front side bus agents and if used, must connect the appropriate pins of all such agents. If the BINIT# driver is enabled during power on configuration, BINIT# is asserted to signal any bus condition that prevents reliable future information. Notes 4 If BINIT# observation is enabled during power-on configuration (see Figure 7.
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Table 20. Name BR0# BR[1:3]#1 Signal Definitions (Sheet 3 of 9) Type Description Notes I/O BR[3:0]# (Bus Request) drive the BREQ[3:0]# signals in the system. The BREQ[3:0]# signals are interconnected in a rotating manner to individual processor pins. The tables below provide the rotating interconnect between the processor and bus signals for 2-way systems.
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Table 20. Name DBI[3:0]# Signal Definitions (Sheet 4 of 9) Type Description Notes I/O DBI[3:0]# are source synchronous and indicate the polarity of the D[63:0]# signals. The DBI[3:0]# signals are activated when the data on the data bus is inverted. If more than half the data bits, within a 16-bit group, would have been asserted electronically low, the bus agent may invert the data bus signals for that particular sub-phase for that 16-bit group.
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Table 20. Signal Definitions (Sheet 5 of 9) Name Type Description Notes FERR#/PBE# O FERR#/PBE# (floating-point error/pending break event) is a multiplexed signal and its meaning is qualified by STPCLK#. When STPCLK# is not asserted, FERR#/PBE# indicates a floating-point error and will be asserted when the processor detects an unmasked floating-point error.
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Table 20. Name LINT[1:0] Signal Definitions (Sheet 6 of 9) Type Description Notes I LINT[1:0] (Local APIC Interrupt) must connect the appropriate pins of all front side bus agents. When the APIC functionality is disabled, the LINT0/INTR signal becomes INTR, a maskable interrupt request signal, and LINT1/NMI becomes NMI, a non-maskable interrupt. INTR and NMI are backward compatible with the signals of those names on the Pentium® processor. Both signals are asynchronous.
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Table 20. Name REQ[4:0]# RESET# Signal Definitions (Sheet 7 of 9) Type Description Notes I/O REQ[4:0]# (Request Command) must connect the appropriate pins of all processor front side bus agents. They are asserted by the current bus owner to define the currently active transaction type. These signals are source synchronous to ADSTB[1:0]#. Refer to the AP[1:0]# signal description for details on parity checking of these signals.
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Table 20. Name Signal Definitions (Sheet 8 of 9) Type Description TCK I TCK (Test Clock) provides the clock input for the processor Test Bus (also known as the Test Access Port). TDI I TDI (Test Data In) transfers serial test data into the processor. TDI provides the serial input needed for JTAG specification support. TDO O TDO (Test Data Out) transfers serial test data out of the processor. TDO provides the serial output needed for JTAG specification support.
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Table 20. Name Signal Definitions (Sheet 9 of 9) Type Description VIDPWRGD I The processor requires this input to determine that the supply voltage for BSEL[1:0] and VID[5:0] is stable and within specification. VSSA I VSSA provides an isolated, internal ground for internal PLL’s. Do not connect directly to ground. This pin is to be connected to VCCA and VCCIOPLL through a discrete filter circuit. VTT P The front side bus termination voltage input pins. Refer to Table 9 for further details.
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5.0 Pin List 5.1 Low Voltage Intel® Xeon™ Processor with 800 MHz System Bus Pin Assignments This section provides sorted pin lists in Table 21 and Table 22. Table 21 is a listing of all processor pins ordered alphabetically by pin name. Table 22 is a listing of all processor pins ordered by pin number.
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5.1.1 Pin Listing by Pin Name Table 21. Pin Listing by Pin Name (Sheet 1 of 8) Pin Name Pin No. Signal Buffer Type Direction Pin Name Pin No.
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Table 21. Pin Listing by Pin Name (Sheet 2 of 8) Pin No. Signal Buffer Type Direction Pin No.
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Table 21. Pin Listing by Pin Name (Sheet 3 of 8) Pin Name MCERR# Pin No. D7 Signal Buffer Type Direction Common Clk I/O TCK Pin Name Pin No.
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Table 21. Pin Name VCC Pin Listing by Pin Name (Sheet 4 of 8) Pin No. D29 Signal Buffer Type Power/Other Direction Pin Name VCC Pin No.
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Table 21. Pin Name VCC Pin Listing by Pin Name (Sheet 5 of 8) Pin No. P6 Signal Buffer Type Power/Other Direction Pin Name VCC Pin No.
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Table 21. Pin Listing by Pin Name (Sheet 6 of 8) Pin No.
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Table 21. Pin Name Pin Listing by Pin Name (Sheet 7 of 8) Pin No. VSS K28 VSS VSS Signal Buffer Type Direction Pin Name Pin No.
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Table 21. Pin Name VSS Pin Listing by Pin Name (Sheet 8 of 8) Pin No. Y1 Signal Buffer Type Direction Pin Name Pin No.
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5.1.2 Pin Listing by Pin Number Table 22. Pin Listing by Pin Number (Sheet 1 of 8) Pin No. Pin Name Signal Buffer Type Direction Output Pin No.
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Table 22. Pin No. C15 Pin Listing by Pin Number (Sheet 2 of 8) Pin Name A15# Signal Buffer Type Direction Source Sync I/O Pin No.
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Table 22. Pin No. Pin Listing by Pin Number (Sheet 3 of 8) Pin Name Signal Buffer Type Direction Power/Other Pin No.
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Table 22. Pin No. Pin Listing by Pin Number (Sheet 4 of 8) Pin Name Signal Buffer Type Power/Other Direction Pin No.
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Table 22. Pin No. P5 Pin Listing by Pin Number (Sheet 5 of 8) Pin Name Signal Buffer Type Direction Pin No.
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Table 22. Pin No. Pin Listing by Pin Number (Sheet 6 of 8) Pin Name Signal Buffer Type Direction Power/Other Pin No.
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Table 22. Pin No. Pin Listing by Pin Number (Sheet 7 of 8) Pin Name Signal Buffer Type Direction AA26 VCC Power/Other AA27 D1# Source Sync AA28 N/C N/C AA29 N/C N/C N/C AA30 VSS Power/Other AA31 VCC Power/Other AB1 VSS Power/Other Pin No.
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Table 22. Pin No. Pin Listing by Pin Number (Sheet 8 of 8) Signal Buffer Type Direction D38# Source Sync I/O AD14 D39# Source Sync I/O AD15 VSS Power/Other AD16 COMP0 Power/Other AD17 VSS Power/Other AD18 D36# Source Sync AD19 D30# Source Sync AD20 VCC Power/Other AD21 D29# AD22 AD23 AD13 Pin Name Input Pin No.
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6.0 6.1 Thermal Specifications Package Thermal Specifications The Low Voltage Intel® Xeon™ processor with 800 MHz system bus requires a thermal solution to maintain temperatures within operating limits. Any attempt to operate the processor outside these operating limits may result in permanent damage to the processor and potentially other components within the system. As processor technology changes, thermal management becomes increasingly crucial when building computer systems.
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The upper point of the thermal profile consists of the Thermal Design Power (TDP) defined in Table 23 and the associated TCASE value. It should be noted that the upper point associated with the Thermal Profile (x = TDP and y = TCASE_MAX @ TDP) represents a thermal solution design point. In actuality the processor case temperature will never reach this value due to TCC activation (see Figure 12).
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Figure 12. Low Voltage Intel® Xeon™ Processor with 800 MHz System Bus Thermal Profile 100 TCASE MAX @ 90 TDP 80 Thermal Profile Y = 0.56 * x + 55 Tcase [°C] 70 60 50 40 30 20 10 0 0 5 10 15 20 25 30 35 Power [W] 40 45 50 55 60 TDP NOTES: 1. Please refer to Table 24 for discrete points that constitute the thermal profile. 2.
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6.1.2 Thermal Metrology The maximum case temperatures (TCASE) are specified in Table 23 and Table 24, and measured at the geometric top center of the processor integrated heat spreader (IHS). Figure 13 illustrates the location where TCASE temperature measurements should be made. For detailed guidelines on temperature measurement methodology, refer to the appropriate thermal/mechanical design guide. Figure 13. Case Temperature (TCASE) Measurement Location 21.25 mm [0.
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6.2.2 On-Demand Mode The processor provides an auxiliary mechanism that allows system software to force the processor to reduce its power consumption. This mechanism is referred to as “On-Demand” mode and is distinct from the Thermal Monitor feature. On-Demand mode is intended as a means to reduce system level power consumption. Systems using the Low Voltage Intel® Xeon™ processor with 800 MHz system bus must not rely on software usage of this mechanism to limit the processor temperature.
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6.2.5 THERMTRIP# Signal Pin Regardless of whether or not Thermal Monitor is enabled, in the event of a catastrophic cooling failure, the processor will automatically shut down when the silicon has reached an elevated temperature (refer to the THERMTRIP# definition in Table 20). At this point, the system bus signal THERMTRIP# will go active and stay active as described in Table 20. THERMTRIP# activation is independent of processor activity and does not generate any bus cycles. 6.2.
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Table 26.
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7.0 Features 7.1 Power-On Configuration Options Several configuration options can be configured by hardware. The Low Voltage Intel® Xeon™ processor with 800 MHz system bus samples its hardware configuration at reset, on the active-toinactive transition of RESET#. For specifics on these options, please refer to Table 14. The sampled information configures the processor for subsequent operation. These configuration options cannot be changed except by another reset.
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Due to the inability of processors to recognize bus transactions during the Sleep state, multiprocessor systems are not allowed to simultaneously have one processor in Sleep state and the other processors in Normal or Stop-Grant state. 7.2.1 Normal State This is the normal operating state for the processor. 7.2.2 HALT Power-Down State HALT is a low power state entered when all logical processors have executed the HALT or MWAIT instruction.
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Figure 14.
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7.2.3 Stop-Grant State When the STPCLK# pin is asserted, the Stop-Grant state of the processor is entered 20 bus clocks after the response phase of the processor-issued ° Acknowledge special bus cycle. Once the STPCLK# pin has been asserted, it may only be deasserted once the processor is in the ° state. For the Low Voltage Intel® Xeon™ processor with 800 MHz system bus, both logical processors must be in the ° state before the deassertion of STPCLK#.
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7.2.5 Sleep State The Sleep state is a very low power state in which each processor maintains its context, maintains the phase-locked loop (PLL), and has stopped most of internal clocks. The Sleep state can only be entered from Stop-Grant state. Once in the Stop-Grant state, the processor will enter the Sleep state upon the assertion of the SLP# signal. The SLP# pin has a minimum assertion of one BCLK period. The SLP# pin should only be asserted when the processor is in the ° state.
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8.0 Debug Tools Specifications Please refer to the ITP700 Debug Port Design Guide for information regarding debug tool specifications. Section 1.2 provides collateral details. 8.1 Debug Port System Requirements The Low Voltage Intel® Xeon™ processor with 800 MHz system bus debug port is the command and control interface for the In-Target Probe (ITP) debugger. The ITP enables run-time control of the processors for system debug.
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8.3.1 Mechanical Considerations The LAI is installed between the processor socket and the processor. The LAI pins plug into the socket, while the processor pins plug into a socket on the LAI. Cabling that is part of the LAI egresses the system to allow an electrical connection between the processor and a logic analyzer. The maximum volume occupied by the LAI, known as the keepout volume, as well as the cable egress restrictions, should be obtained from the logic analyzer vendor.