User's Manual (1.0a)

6-9
Chapter 6: BIOS
DRAM RAPL Configuration
This sub-menu allows you to configure DRAM RAPL Configuration
settings.
DRAM RAPL Baseline
This setting allows you to enable the DRAM RAPL Baseline and its
mode. Options include Disable, DRAM RAPL Mode 0 and DRAM
RAPL Mode 1.
Override BW_LIMIT_TF
This setting allows you to custom tune BW_LIMIT_TF when DRAM
RAPL is enabled. Use the “+” or “-” key on your keyboard’s number
pad to select a value.
DRAM RAPL Extended
Range
Use this setting to Enable or Disable the DRAM RAPL Extended
Range for your system.
Table 6-5. Chipset Configuration Sub-menu
Menu Option Description
North Bridge Configuration
This sub-menu configures North Bridge features and shows
configuration information.
IOH Configuration
This submenu configures Intel VT-d and Intel I/OAT in your system
and configures IOU PCIe port bifurcation controls.
EV DFX Features
Use this setting to Enable or Disable allowing DFX Lock Bits to
remain clear.
IIO0 Configuration This sub-menu allows you to set IIO0 Configuration.
IOU2 (IIO PCIe Port 1)
Selects PCIe port BIfurcation for PCIe Port 1. Options include x4x4,
x8 or Auto.
IOU0 (IIO PCIe Port 2)
Selects PCIe port BIfurcation for PCIe Port 2. Options include
x4x4x4x4, x4x4x8, x8x4x4, x8x8, x16 or Auto.
IOU1 (IIO PCIe Port 3)
Selects PCIe port BIfurcation for PCIe Port 3. Options include
x4x4x4x4, x4x4x8, x8x4x4, x8x8, x16 or Auto.
No PCIe port active
ECO
Use this for workaround settings when no PCIe port is active.
Options include PCU Squelch Exit Ignore Option or Reset the SQ
FLOP by CSR Option.
Socket 0
PCIED00F0 - Port 0/
DMI
Use this submenu for settings related to PCI Express Ports.
Link Speed
This setting specifies the link speed for the PCI-E port. Options
include Auto, Gen 1 (2.5 GT/s) or Gen 2 (5 GT/s)
PCI-E Port
DeEmphasis
This setting allows you to de-emphasize control for this PCI-E port.
Options include -6.0 dB or -3.5 dB.
PCI-e Port Link
Information
This is static information for your PCI-E link and includes PCI-E Port
Link Status, PCI-E Port Link Max and PCI-E Port Link Speed.
PCI-E Port L0s Exit
Latency
This setting allows you to specify the length of time this port requires
to complete transition from L0s to L0. The default and only option is
4uS-8uS.
Table 6-4. CPU Configuration Submenu (Continued)
Menu Option Description