User's Manual (1.0)

Chapter 7: AMI BIOS
7-7
codes to overwhelm the processor to damage the system during an attack. This
feature is used in conjunction with the items: "Clear MCA," "VMX," "Enable SMX,"
and "Lock Chipset" for Virtualization media support. The options are Enable and
Disable. (Refer to Intel and Microsoft websites for more information.)
PPIN Control
Select Unlock/Enable to use the Protected-Processor Inventory Number (PPIN) in
the system. The options are Unlock/Enable and Unlock/Disable.
Hardware Prefetcher (Available when supported by the CPU)
If set to Enable, the hardware prefetcher will prefetch streams of data and instruc-
tions from the main memory to the L2 cache to improve CPU performance. The
options are Disable and Enable.
Adjacent Cache Prefetch (Available when supported by the CPU)
Select Enable for the CPU to prefetch both cache lines for 128 bytes as comprised.
Select Disable for the CPU to prefetch both cache lines for 64 bytes. The options
are Disable and Enable.
Note: Please reboot the system for changes on this setting to take effect.
Please refer to Intel’s website for detailed information.
DCU (Data Cache Unit) Streamer Prefetcher (Available when supported by
the CPU)
If set to Enable, the DCU Streamer Prefetcher will prefetch data streams from the
cache memory to the DCU (Data Cache Unit) to speed up data accessing and
processing to enhance CPU performance. The options are Disable and Enable.
DCU IP Prefetcher
If set to Enable, the IP prefetcher in the DCU (Data Cache Unit) will prefetch IP
addresses to improve network connectivity and system performance. The options
are Enable and Disable.
Direct Cache Access (DCA)
Select Enable to use Intel DCA (Direct Cache Access) Technology to improve the
efciency of data transferring and accessing. The options are Auto, Enable, and
Disable.
X2APIC (Advanced Programmable Interrupt Controller)
Based on Intel's Hyper-Threading architecture, each logical processor (thread) is
assigned 256 APIC IDs (APIDs) in 8-bit bandwidth. When this feature is set to En-
able, the APIC ID will be expanded from 8 bits (X2) to 16 bits to provide 512 APIDs
to each thread to enhance CPU performance. The options are Disable and Enable.