Datasheet

7-12
S
UPERSERVER 6014H-32 User's Manual
No Execute Mode Memory Protection (*Available when supported by the
CPU.)
Enable this feature to enable the functionality of Execute Disable Bit and allow
the processor to classify areas in the memory where an application code can
execute and where it cannot, and thus preventing a worm or a virus from inserting
and creating a fl ood of codes that will overwhelm the processor or damage the
system during an attack. (*Note: this feature is available when your OS and your
CPU support the function of Execute Disable Bit.) The options are Disabled and
Enabled. (*Note: For more information regarding hardware/software support for
this function, please refer to Intel's and Microsoft's web sites.)
Thermal Management 2 (*Available when supported by the CPU.)
If enabled, this feature allows you to select between Thermal Manager 1 and Thermal
Manager 2. Set to Disable to activate the function of TM1, allowing the CPU to
regulate its power consumption based upon the modulation of the CPU Internal
clock when the CPU temperature reaches a pre-defi ned overheat threshold. Set
to Enable to activate the function of TM2, which will allow the CPU to reduce its
power consumption by lowering the CPU frequency and the CPU voltage when the
CPU temperature reaches a pre-defi ned overheat threshold. (*Note: please refer
to Intel's web site for detailed information.)
Adjacent Cache Line Prefetch
The CPU fetches the cache line for 64 bytes if Dtisabled. The CPU fetches both
cache lines for 128 bytes as comprised if Enabled.
Processor Power Management (*Available when supported by the CPU.)
This feature allows the user to determine the processor power management
mode. If set to C States only, the processor power will be controlled through CPU
power states in the ACPI setting. Select "GV1/GV3 only" to enable the function of
DBS (Demand Based Switching) which will allow the user to confi gure CPU power
management in the OS. If set to Disabled, C States and GV1/GV3 are disabled. If
set to Enabled, C States and GV1/GV3 are Enabled. (*Note: please refer to Intel's
web site for detailed information.)