User's Manual (1.0b)

Chapter 1: Overview

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1-2 Processor/PCH Platform Overview

Built upon the functionality and capability of the Intel E7 series processor(s) and

the 602J PCH, the X10QBi system provides support for quad-processor-based

HPC/Cluster/Database server platforms.

With the Intel QuickPath interconnect (QPI) controller built in, the E7 series proces-

sor offers a point-to-point system interconnect interface, greatly enhancing system

performance by utilizing serial link interconnections, which allows for increased

bandwidth and scalability.

The 602J PCH provides an Interface between the QPI-based processor and PCI-

Express components. Each processor supports full-width, bidirectional intercon-

nects at the speeds of 6.4 GT/s, 7.2 GT/s, and 8.0 GT/s. Each QPI link consists

of 20 pairs of unidirectional differential lanes for data transmission in addition to

a differential forwarding clock. The x16 PCI Express Gen 3 connections can also

be congured as x8, x4, and x2 links to comply with the PCI-E Base Specica-

tion, Rev. 2.0. These PCI-E Gen 3 lanes support peer-to-peer read-and-write

transactions.

The 602J PCH also offers a wide range of ESI, Intel® I/OAT Gen 3, Intel VT-d, and

RAS (Reliability, Availability and Serviceability) support. The features supported

include memory interface ECC, x4/x8 Single Device Data Correction (SDDC),

Flow-through CRC (Cyclic Redundancy Check), parity protection, out-of-band

Main Features of the 602J PCH Chip

•Full-connectivity (with four Intel® QuickPath Interconnects and up to ten cores

in each socket with 24MB of shared last level (L3) cache supported)

•CPU-integrated memory controller with support of DDR-3 1600 MHz RDIMM/

LRDIMM modules

•Virtualization Technology

•44-bit physical address and 48-bit virtual address supported