User's Manual (1.0b)

Chapter 4: AMI BIOS

4-7

execute and where it cannot, thus preventing a worm or a virus from ooding illegal

codes to overwhelm the processor or damage the system during an attack. This

feature is used in conjunction with the items: "Clear MCA," "VMX," "Enable SMX,"

and "Lock Chipset" for Virtualization media support. The default setting is Enable.

(Refer to Intel and Microsoft websites for more information.)

VMX

Select Enable for CPU-related Virtualization support. This feature is used in conjunc-

tion with the items: "Clear MCA," "Enable SMX," and "Lock Chipset" for Virtualization

media support. The options are Enable and Disable.

Enable SMX

Select Enable for Safer Mode Extensions (SMX) support to enhance data security

in the processor. This feature is used in conjunction with the items: "Clear MCA,"

"VMX," and "Lock Chipset" for Virtualization media support. The options are En-

able and Disable.

Lock Chipset

Select Enable to lock chipset register tables and set the register tables to "read-only"

to prevent new data being written into the processor to ensure system security. This

feature is used in conjunction with the items: "Clear MCA," "VMX," and "Enable

SMX" for Virtualization media support. The options are Enable and Disable.

BIST Selection

Select Enable to congure Built-In_Self_Test (BIST) settings, which will allow the

system to perform BIST testing on the processors at bootup. The options are En-

able and Disable.

Hardware Prefetcher (Available when supported by the CPU)

If set to Enable, the hardware prefetcher will prefetch streams of data and instruc-

tions from the main memory to the L2 cache to improve CPU performance. The

options are Disable and Enable.

Adjacent Cache Line Prefetch (Available when supported by the CPU)

Select Enable for the CPU to prefetch both cache lines for 128 bytes as comprised.

Select Disable for the CPU to prefetch both cache lines for 64 bytes. The options

are Disable and Enable.

Note: Please reboot the system for changes on this setting to take effect.

Please refer to Intel’s web site for detailed information.