User's Manual (1.0b)
Chapter 4: AMI BIOS
4-23
DDR Voltage Level
Select Force to 1.50V to force all DDR3 memory modules to operate at 1.50V.
Select Force to 1.35V to force all DDR3 memory modules to operate at 1.35V.
The options are Auto, Force to 1.50V, and Force to 1.35V.
Advanced Clk (Clock) Training
Select Enable for Advanced Clock Training support, which will allow the memory
command line to be synchronized with the clock line to enhance memory perfor-
mance. The options are Enable and Disable.
Perbit (Per-bit) Deskew Training
Select Enable for Perbit Deskew Training support, which will allow the memory
controller to include various adjustable delay circuits in both Read and Write
paths on a per-bit base for effective memory interface to maximize memory
performance. The options are Disable and Enable.
ODT Timing Mode
Use this feature to set the ODT (On-Die Termination) Timing mode for the
memory controller to enhance memory performance. The options are Aggres-
sive Timing and Conservative Timing.
MxB Rank Sharing Mapping
Use this feature to select the address-mapping setting for memory-rank sharing
to enhance extended multimedia platform performance. he options are Maximum
Performance and Maximum Margin.
DIMM Vref. (Voltage Reference) Circuit
This feature allows the user to decide how to congure the voltage reference
point (gate) for a DDR3 memory module. The options are Internal and External.
BIOS VMSE Reset
If this feature is set to Enable, BIOS settings pertaining to the Intel Scalable
Memory Interconnect 2 (Intel SMI 2) controller will be reset to improve system
performance. The options are Disable and Enable.
Save JCK Error Longs
Select Enable to save the JCK Error log at each system reset caused by system
rmware. The options are Enable and Disable.
Phase Shedding
Select Enabled to enable Static Phase-Shedding support for DDR3 memory
voltage regulators to improve memory performance. The options are Auto,
Disabled and Enabled.