User Manual
Table Of Contents
- Preface
- Chapter 1 Introduction
- Chapter 2 Installation
- 2-1 Standardized Warning Statements
- 2-2 Static-Sensitive Devices
- 2-3 Motherboard Installation
- 2-4 Memory Support
- 2-5 Connectors/IO Ports
- 2-6 Connecting Cables
- ATX PWR, DC PWR and HDD PWR Connectors (JPW1, PJ1, J6)
- Fan Headers (FAN1 ~ FAN4) (FAN4 is available on PCB 2.00 only)
- Chassis Intrusion
- System Management Bus Header
- DOM PWR Connector
- TPM Header/Port 80 Header
- Overheat LED Header
- Speaker
- Standby Power
- I-SGPIO1/I-SGPIO2
- NVMe I2C Header
- Power SMBus (I2C) Connector (available on PCB 2.00 only)
- System Management Bus Header
- GPIO Header
- ATX PWR, DC PWR and HDD PWR Connectors (JPW1, PJ1, J6)
- 2-7 Jumper Settings
- 2-8 Onboard Indicators
- 2-9 SATA Connections
- Chapter 3 Troubleshooting
- Chapter 4 BIOS
- Appendix A BIOS Error Beep Codes
- Appendix B Software Installation Instructions
- Appendix C UEFI BIOS Recovery Instructions
- Appendix D Dual Boot Block
Chapter 4: AMI BIOS
4-13
Data Scrambling
Select Enabled to enable data scrambling to enhance system performance and
data integrity. The options are Auto, Disabled and Enabled.
DRAM RAPL Baseline
Use this feature to set the run-time power-limit baseline for DRAM modules. The
options are Disable, DRAM RAPL Mode 0, and DRAM RAPL Mode 1.
Set Throttling Mode
Throttling improves reliability and reduces power consumption in the processor
via automatic voltage control during processor idle states. The options are Dis-
abled and CLTT (Closed Loop Thermal Throttling).
A7 Mode
Select Enabled to support the A7 (Addressing) mode to improve memory perfor-
mance. The options are Enable and Disable.
DIMM Information
This item displays the status of a DIMM module specied by the user.
• DIMMA1
• DIMMB1
• DIMMA2
• DIMMB2
Memory RAS (Reliability_Availability_Serviceability)
Conguration
Use this submenu to congure the following Memory RAS settings.
Patrol Scrub
Patrol Scrubbing is a process that allows the CPU to correct correctable memory
errors detected on a memory module and send the correction to the requestor
(the original source). When this item is set to Enabled, the IO hub will read and
write back one cache line every 16K cycles, if there is no delay caused by internal
processing. By using this method, roughly 64 GB of memory behind the IO hub
will be scrubbed every day. The options are Enable and Disable.