User's and BIOS Manual (1.1a)

Chapter 1: Introduction
1-9
1-2 Chipset Overview
Built upon the functionality and the capability of the 5000X chipset, the X7DA8+/
X7DAE+ motherboard provides the performance and feature set required for dual
processor-based servers with confi guration options optimized for communications,
presentation, storage and computation applications or for use as workstations. The
5000X chipset supports single or dual Xeon 64-bit Quad-Core/Dual-Core proces-
sors with front side bus speeds of up to 1.333 GHz. The chipset consists of the
5000X Memory Controller Hub (MCH), the Enterprise South Bridge 2 (ESB2), and
the I/O subsystem (PXH-V).
The 5000X MCH chipset is designed for symmetric multiprocessing across two
independent front side bus interfaces. Each front side bus uses a 64-bit wide, 1.333
GHz data bus. The MCH chipset connects up to 8 Fully Buffered DIMM modules,
providing a total of 32.0 GB/s for DDR2 667/533 memory. The MCH chipset also
provides three x8 PCI-Express and one x4 ESI interface to the ESB2. In addition,
the 5000X chipset offers a wide range of RAS features, including memory inter-
face ECC, x4/x8 Single Device Data Correction, CRC, parity protection, memory
mirroring and memory sparing.
Xeon Quad-Core/Dual-Core Processor Features
Designed to be used with conjunction of the 5000X chipset, the Xeon Quad-Core/
Dual-Core Processors provide a feature set as follows:
The Xeon Quad-Core/Dual-Core Processors
*L1 Cache Size: Instruction Cache (32KB/16KB), Data Cache (32KB/24KB)
*L2 Cache Size: 4MB/2MB (per core)
*Data Bus Transfer Rate: 8.5 GB/s
*Package: FC-LGA6/FC-LGA4, 771 Lands