Datasheet

Chapter 1: Introduction
1-9
1-2 Chipset Overview
Built upon the functionality and the capability of the 5000X chipset, the X7DAL-E+
motherboard provides the performance and feature set required for dual proces-
sor-based workstations with confi guration options optimized for communications,
presentation, storage and computation applications or for use as workstations.
The 5000X chipset supports a single or two Xeon 64-bit Dual-Core or Quad-Core
processor(s) with front side bus speeds of up to 1333 MHz. The chipset consists
of the 5000X Memory Controller Hub (MCH), and the Enterprise South Bridge 2
(ESB2).
The 5000X MCH chipset is designed for symmetric multiprocessing across two
independent front side bus interfaces. Each front side bus uses a 64-bit wide, 1.333
GHz data bus. The MCH chipset connects supports Fully Buffered DIMM modules,
providing a total memory of up to 24.0 GB. In addition, the 5000X chipset offers a
wide range of RAS features, including memory interface ECC, x4/x8 Single Device
Data Correction, CRC, parity protection, memory mirroring and memory sparing.
The Xeon Dual-Core and Quad-Core Processor Features
Designed to be used with conjunction of the 5000X chipset, the Xeon Quad-Core/
Quad-Core Processor provides a feature set as follows:
The Xeon Dual Core Processors
*L1 Cache Size: Instruction Cache (32KB/16KB), Data Cache (32KB/24KB)
*L2 Cache Size: 4MB (2MB per core)
*Data Bus Transfer Rate: 8.5 GB/s
*Package: FC-LGA6/FC-LGA4, 771 Lands
The Xeon Quad Core Processors
*L1 Cache Size: Instruction Data Cache (32KB per core)
*L2 Cache Size: Shared 4MB per die (8MB Total Cache per processor)
*Data Bus Transfer Rate: 8.5 GB/s