User's and BIOS Manual (1.2)

Chapter 4: BIOS

4-11

Advanced Chipset Control

Access the submenu to make changes to the following settings.

Warning: Take caution when changing the Advanced settings. An incorrect

setting, a very high DRAM frequency or an incorrect DRAM timing may make

the system unstable. When this occurs, revert to the default setting.

SERR Signal Condition

This setting speciﬁ es the ECC Error conditions that an SERR# is to be asserted.

The options are None, Single Bit, Multiple Bit, and Both.

4GB PCI Hole Granularity

This feature allows you to select the granularity of PCI hole for PCI slots. If MTRRs

are not enough, this option may be used to reduce MTRR occupation. The options

are: 256 MB, 512 MB, 1GB and 2GB.

Memory Branch Mode

This option determines how the two memory branches operate. System address

space can either be interleaved between the two branches or Sequential from one

branch to another. Mirror mode allows data correction by maintaining two copies

of data in two branches. Single Channel 0 allows a single DIMM population during

system manufacturing. The options are Interleave, Sequential, Mirroring, and

Single Channel 0.

Branch 0/1 Rank Interleave

Select enable to enable Memory Interleaving support for Branch 0/ Bramch1 memory

in order to enhance system performance. The options are 1:1, 2:1 and 4:1.

Branch 0/1 Rank Sparing

Select enable to enable Rank Sparing support for Branch 0/ Bramch1 memory in

order to enhance data security. The options are Enabled and Disabled.

Enhanced x8 Detection

Select Enabled to enable Enhanced x8 DRAM UC Error Detection. The options

are Disabled and Enabled.

High Bandwidth FSB

Select Enabled to enable high bandwidth FSB support. The options are Enabled

and Disabled.

High Temperature DRAM Operation

When set to Enabled, the BIOS will refer to the SPD table to set the maximum

DRAM temperature. If disabled, the BIOS will set the maximum DRAM temperature

based on a predeﬁ ned value. The options are Enabled and Disabled.