User's and BIOS Manual (1.1)
Chapter 2: Installation
2-23
SP1
+
+
B1
JBT1
IPMB
JD1
JPW1
JPW2
JPI2C
JWOL
JWF1
JF1
FAN2
FAN1
FAN5
FAN3
FAN4
T-SGPIO1 T-SGPIO2
JI2C1
JI2C2
JWOR
JL1
3
JPUSB1
JLED
JPL1
JPL2
JPG1
LE1
C
C
LE7
J*
W83627DHG
IDT
89HI0524G2PS
PCH
Hermon
SLOT7 PCI-E 2.0 (2.5GT/s) X1
SLOT6 PCI-E 2.0
SLOT5 PCI-E 2.0 X8
SLOT4 PCI-E 2.0 X8
SLOT3 PCI-E 2.0 (2.5GT/s) X1
USB8/9
FAN2/CPUFAN
USB4
USB5
FAIL
PWR
DOM PWR
JWOL:
I-SATA4
I-SATA3
UID
DIMM2A
DIMM2BDIMM2CDIMM1B DIMM1A
Chassis Intrusion
Wake on Lan
Wake on Ring
CMOS CLEAR
1-2:ENABLE
2-3:DISABLE
JPL2:LAN2
JPL1:LAN1
2-3:DISABLE
1-2:ENABLE
JPB:BMC
JPI2C:PWR I2C
JSPK:Buzzer/Speaker
COM2
FLOPPY
DDR3 1066/1333 UDIMM/RDIMM required
JL1:
LAN1/LAN2
JPUSB1:B/P USB WAKE UP
1-2:ENABLE
2-3:DISABLE
JI2C1/JI2C2
USB6/7
2-3:Disable
1-2:Enable
CPU
JLED:Power LED
OFF:Disable
ON:Enable
2-3:DISABLE
1-2:ENABLE
JF1
ON
LED LED
PWRHDD
NIC1
NIC2
OH/FF
RST
PWR
I-SATA2
I-SATA1
I-SATA0
I-SATA5
SLOT2 PCI-E 2.0 (2.5GT/s) X4 (IN X8 SLOT)
SLOT1 PCI 33MHz
DIMM1C
JPG1: VGA
KB/MOUSE
VGA
COM1
IPMI_LAN
USB0/1
USB2/3
X8SIA
Front Control Panel
JF1 contains header pins for various buttons and indicators that are normally lo-
cated on a control panel at the front of the chassis. These connectors are designed
specically for use with Supermicro server chassis. See the gure below for the
descriptions of the various control panel buttons and LED indicators. Refer to the
following section for descriptions and pin denitions.
JF1 Header Pins
Power Button
OH/Fan Fail LED
1
NIC1 LED
Reset Button
2
HDD LED
Power LED
Reset
PWR
LED_Anode+
LED_Anode+
LED_Anode+
Ground
Ground
Power Fail LED
NIC2 LED
LED_Anode+
LED_Anode+
LED_Anode+
Pin 15Pin 16
Pin 1
Pin 2