User's Manual (1.0c)

Chapter 2: Installation
2-27
JLAN2
3
JSTBY
JCOM1
R625
MH7
MH1
MH5
41
FAN1
41
FAN2
4
1
FAN3
41
FAN4
41
FANA
JVR6
3
JVR5
1
3
JVR4
1
3
JVR3
1
3
JPB1
1
3
JPG1
1
JPL1
1
JPL2
JVR1
1
3
JVR2
1 3
JWD1
1
3
JPUSB1
1
JPME_RCV1
3
JPBIOS_RCV1
1
3
DP3
A
C
JI2C1
JI2C2
1
JOH1
1
JCF1
JL1
3-SGPIO2
1
2
7 8
3-SGPIO1
1
2
7
8
T-SGPIO1
2
7
8
T-SGPIO2
1
2
7
8
DIMM_C1
JUSB2
4
PCIX1
PCIX2
PCIX3
JPW1
1
12
24
JBT1
JPI2C1
1
5
SP1
+
PCIE6
PCIE5
PCIE4
X_BT1
JPW2
UID_LED
A
C
UID_SW
1
2
JTPM1
1
2
19
20
SAS4
SAS5 SAS6
SAS7 I-SATA2I-SATA3
I-SATA4
I-SATA5
JKBMS1
+
U8
JWF1
1
3
JTAG1
JD1
1
7
JF1
1
2
19
20
JVGA
JIPMB1
I-SATA1
I-SATA0
MAC CODE
MAC CODE
REV:1.01
Tested to Comply With FCC Standards FOR HOME OR OFFICE USE
DESIGNED IN USA
SAS CODE
JCOM2
1
5
6
9
JUSB45
2
7
10
JUSB67
1
2
7
JUSB89
1
2
7
10
JRK1
Pin3:PCH_DYN_SKU
Pin2:Ground
OFF:NORMAL
ON:ME IN FORCE UPDATA MODE
I-Button Header 1
Pin1:RAID_KEY_PCH
OFF:NORMAL
ON:RECOVER BIOS
UID
TPM/PORT80
JIPMB1
P1-DIMM4A P1-DIMM4B
P1-DIMM3A P1-DIMM3B
P1-DIMM2A
P1-DIMM2B
P1-DIMM1B P1-DIMM1A
I-SATA5
I-SATA4
I-SATA3 I-SATA2
I-SATA1
I-SATA0
2-3 ENable
Power Flash
KB/MOUSE
X9SRi
JPUSB1:USB Wake Up
1-2 Disable
PWRI2C
JF1
RST
ON
PWR
PWR
FF
FAIL
HDD NIC
1 2
NIC
OH
LED
NMI
PWR
X
PWR LED
SPEAKER
1-3:
4-7:
JD1:
2-3:NMI
JWD1:Watch Dog
1-2:RST
LAN1
LAN2
JPL1/2: LAN
2-3 Disable
1-2 Enable
FAN4
VGA
COM1
USB0/1
INTRUSION
CHASSIS
OFF: SLAVE ON: MASTER JCF1:Compact Flash
Compact
SAS1/SAS3
SAS0/SAS2
3-SGPIO23-SGPIO1
Connect to IPMI
USB2
USB8/9
USB4/5
USB6/7
2-3 Disable
JPB: BMC
1-2 Enable
JSTBY : Wake on Lan
COM2
1-2 Enable 2-3 Disable JPG1: VGA
OFF:DISABLE ON: ENABLE
I2C Bus for PCI slot
JI2C1/JI2C2
SLOT4 PCI-E 3.0 X8 (IN X16)
SLOT5 PCI-E 2.0 X4 (IN X16)
SLOT6 PCI-E 3.0 X16
SLOT3 PCI-X 133/100MHZ
SLOT1 PCI-X 133/100MHZ
SLOT2 PCI-X 133/100MHZ
CLOSE 1st
OPEN 1st
JPW2
C
Serial_Link-SGPIO
Pin Denitions
Pin# Denition Pin Denition
1 NC 2 NC
3 Ground 4 DATA Out
5 Load 6 Ground
7 Clock 8 NC
T-SGPIO 1/2 Headers (T-SGPIO)
Two T-SGPIO (Serial-Link General
Purpose Input/Output) headers are
located near the SATA connectors
on the motherboard. These headers
are used to communicate with the
enclosure management chip in the
system. See the table on the right
for pin denitions. Refer to the board
layout below for the locations of the
headers.
NC: No Connections
A. T-SGPIO 1
B. T-SGPIO 2
C. 3-SGPIO 1
D. 3-SGPIO 2
E. TPM Header
A
B
T-SGPIO 1/2 & 3-SGPIO 1/2 Headers
Two T-SGPIO (Serial-Link General Pur-
pose Input/Output) headers are located
next to the I-SATA Ports on the mother-
board. Additionally, two 3-SGPIO ports
(for SAS) are also located next to JUSB
8/9 . These headers are used to com-
municate with the enclosure manage-
ment chip in the system. See the table
on the right for pin denitions. Refer to
the board layout below for the locations
of the headers.
Trusted Platform Module Header
Pin Denitions
Pin # Denition Pin # Denition
1 LCLK 2 GND
3 LFRAME 4 No Pin
5 LRESET 6 VCC5
7 LAD3 8 LAD2
9 VCC3 10 LAD1
11 LAD0 12 GND
13 SMBCLK 14 SMBDAT
15 SB3V 16 SERIRQ
17 GND 18 CLKRUN
19 LPCPD 20 LDRQ1
TPM Header (JTPM1)
This header is used to connect a
Trusted Platform Module (TPM), which
is available from a third-party vendor.
A TPM is a security device that sup-
ports encryption and authentication
in hard drives. It enables the moth-
erboard to deny access if the TPM
associated with the hard drive is not
installed in the system. See the table
on the right for pin denitions.
D
E