SB16C1053APCI PCI Target Controller with 2 Serial, 1 Parallel and MIO Bus PCI to 2S+1P with MIO Bus Bridge JULY 2013 REV 1.06 PCI Target Interface Controller SB16C1053APCI Revision 1.06 SystemBase Co., Ltd.
SB16C1053APCI PCI Target Controller with 2 Serial, 1 Parallel and MIO Bus PCI to 2S+1P with MIO Bus Bridge JULY 2013 REV 1.06 CONTENTS 1. Description ..................................................................................................................................... 7 2. Features ......................................................................................................................................... 7 2.1 PCI Interface .......................................................
SB16C1053APCI PCI Target Controller with 2 Serial, 1 Parallel and MIO Bus PCI to 2S+1P with MIO Bus Bridge JULY 2013 REV 1.06 8.1.9 Header Type ............................................................................................................... 27 8.1.10 BIST(Built-In Self Test) .............................................................................................. 27 8.1.11 Base Address Registers ............................................................................................
SB16C1053APCI PCI Target Controller with 2 Serial, 1 Parallel and MIO Bus PCI to 2S+1P with MIO Bus Bridge JULY 2013 REV 1.06 11.2 Hardware Flow Control ........................................................................................................ 47 11.2.1 Auto-RTS .................................................................................................................. 47 11.2.2 Auto-CTS ....................................................................................................
SB16C1053APCI PCI Target Controller with 2 Serial, 1 Parallel and MIO Bus PCI to 2S+1P with MIO Bus Bridge JULY 2013 REV 1.06 12.19 Auto Toggle Control Register (ATR, Page 3) ........................................................................ 77 12.20 Enhanced Feature Register (EFR, Page 3) ........................................................................... 79 12.21 Special Character Register (SCR, Page 3) ............................................................................ 80 12.
SB16C1053APCI PCI Target Controller with 2 Serial, 1 Parallel and MIO Bus PCI to 2S+1P with MIO Bus Bridge JULY 2013 REV 1.06 16.3 DC Characteristics ............................................................................................................100 16.3.1 PCI PAD 3.3V 66MHz DC Signaling Characteristics ......................................................100 16.3.1 PCI PAD 3.3V 66MHz DC Signaling Characteristics ......................................................100 17.
SB16C1053APCI PCI Target Controller with 2 Serial, 1 Parallel and MIO Bus PCI to 2S+1P with MIO Bus Bridge JULY 2013 REV 1.06 1. Description SB16C1053APCI is a PCI Target Interface Controller with Dual-UART, single Parallel Port TM and MIO Bus . It offers easy PCI Target Card Adapter implementation for serial port and parallel port. SB16C1053APCI provides high performance serial and parallel port communication.
SB16C1053APCI PCI Target Controller with 2 Serial, 1 Parallel and MIO Bus PCI to 2S+1P with MIO Bus Bridge JULY 2013 REV 1.
SB16C1053APCI PCI Target Controller with 2 Serial, 1 Parallel and MIO Bus PCI to 2S+1P with MIO Bus Bridge JULY 2013 REV 1.06 4.
SB16C1053APCI PCI Target Controller with 2 Serial, 1 Parallel and MIO Bus PCI to 2S+1P with MIO Bus Bridge JULY 2013 REV 1.06 5. Applications 5.1 Serial 1-port (1S) Serial 1-port is generally made with SB16C1053APCI (called by 1S Mode). Special logic is not needed to make one serial port since Single-UART is built inside the SB16C1053APCI. Depending on Serial Interface, Transceiver IC of the RS232, RS422 or RS485 needs to be attached for long distance transmission.
SB16C1053APCI PCI Target Controller with 2 Serial, 1 Parallel and MIO Bus PCI to 2S+1P with MIO Bus Bridge JULY 2013 REV 1.06 5.3 Serial 2-port and Parallel 1-port (2S 1P) Serial 2-port and Parallel 1-port (2S1P) is generally made with SB16C1053APCI (called by 2S1P Mode). Special logic is not needed to make one serial port since Dual-UART and IEEE1284 compatible Parallel Port is built inside the SB16C1053APCI.
SB16C1053APCI PCI Target Controller with 2 Serial, 1 Parallel and MIO Bus PCI to 2S+1P with MIO Bus Bridge JULY 2013 REV 1.06 5.5 Serial 4-port (4S) Serial 4-port is generally made with SB16C1053APCI (called by 4S Mode). Especially SB16C1053APCI support 8-bit legacy local bus for extension of additional serial ports. TM SystemBase revised the MIO BUS (Multi-Port I/O Bus) for the extension. Basically Dual-UART is built inside the SB16C1053APCI.
SB16C1053APCI PCI Target Controller with 2 Serial, 1 Parallel and MIO Bus PCI to 2S+1P with MIO Bus Bridge JULY 2013 REV 1.06 6. Pin Configuration CTS0# DCD0# DSR0# RI0# RXD0 DTR0# RTS0# VCC 102 101 100 99 98 97 RSVD0/GPO[1] 105 103 GPO[0] 106 104 WAKEREQ 107 108 NC NC NC GND 109 REQ# 111 110 GNT# 113 112 NC 116 NC RST# 117 INTA# CLK 118 114 PME# 119 115 GND AD[31] 120 VCC 122 121 AD[29] AD[30] 123 125 124 AD[26] AD[27] AD[28] 126 AD[25] 127 128 6.
SB16C1053APCI PCI Target Controller with 2 Serial, 1 Parallel and MIO Bus PCI to 2S+1P with MIO Bus Bridge JULY 2013 REV 1.06 6.2 Pin Description Table 6–1: Pin Description Modem and Serial I/O Interface Name Pin Type Description TXD0 95 O Transmit Data: These pins are individual transmit data output. During the TXD1 87 O local loop-back mode, the TXD output pin is disabled and TXD data is internally connected to the RXD input.
SB16C1053APCI PCI Target Controller with 2 Serial, 1 Parallel and MIO Bus PCI to 2S+1P with MIO Bus Bridge JULY 2013 REV 1.06 111b: RS485 Echo interface is selected. RXEN0#_INTF01 49 I/O These pin are dual mode pins. After power is supplied to the chip, the pin is RXEN1#_INTF11 51 I/O set to input mode for a while and receive INTFx[2:0] input. After that, the pins are set to output mode and outputs RXEN#x as auto toggle.
SB16C1053APCI PCI Target Controller with 2 Serial, 1 Parallel and MIO Bus PCI to 2S+1P with MIO Bus Bridge JULY 2013 REV 1.06 Table 6–1: Pin Description…continued Function Configuration Interfaces Name Pin Type Description SLCT_MIRQ3 71 I These pins works as SLCT in 1P and 2S1P mode and MIRQ3 of MIO Bus 4S and 6S mode. TM in Parallel Port Peripheral Selected: This pin is asserted by peripheral when the peripheral is selected (the peripheral device is on line).
SB16C1053APCI PCI Target Controller with 2 Serial, 1 Parallel and MIO Bus PCI to 2S+1P with MIO Bus Bridge JULY 2013 REV 1.06 Table 6–1: Pin Description…continued Function Configuration Interfaces Name Pin Type Description DIR_INTF12_MA0 63 I/O These pin are dual mode pin. After power is supplied to the chip, the pin is set to input mode for a while and receive INTFx[2:0] input. After that, the pin is set to output mode and outputs DIR or MA0.
SB16C1053APCI PCI Target Controller with 2 Serial, 1 Parallel and MIO Bus PCI to 2S+1P with MIO Bus Bridge JULY 2013 REV 1.06 Table 6–1: Pin Description…continued 2 I C Serial EEPROM Interfaces Name Pin Type Description SCL 52 O Serial EEPROM Clock Output: Connected to SCL of serial EEPROM. SDA 53 I/O Serial EEPROM Data Input/Output: Connected to SDA of serial EEPROM. Name Pin Type Description CLK 118 I PCI Clock: PCI clock provides timing for all transaction on SB16C1053APCI.
SB16C1053APCI PCI Target Controller with 2 Serial, 1 Parallel and MIO Bus PCI to 2S+1P with MIO Bus Bridge JULY 2013 REV 1.06 Table 6–1: Pin Description…continued PCI Interfaces Name Pin Type Description AD[31] 120, T/S Address and Data: These signals are multiplexed on the same pins.
SB16C1053APCI PCI Target Controller with 2 Serial, 1 Parallel and MIO Bus PCI to 2S+1P with MIO Bus Bridge JULY 2013 REV 1.06 IDSEL Table 6–1: 3 I Initialization Device Select: This is used for chip selection during configuration read and write transaction. Pin Description…continued PCI Interfaces Name Pin Type Description DEVSEL# 18 S/T/S Device Select: This signal indicates that the driving device has decoded its address as the target of the current access.
SB16C1053APCI PCI Target Controller with 2 Serial, 1 Parallel and MIO Bus PCI to 2S+1P with MIO Bus Bridge JULY 2013 REV 1.06 MCS0#_PORT0 58 I/O This pin is dual mode pin. After power is supplied to the chip, the pin is set to input mode for a while and receive PORTx[2:0] input. After that, the pin is set TM to MCS0# (output) of MIO Bus in 4S and 6S mode. TM MIO Bus Chip Select 0: This output pin is a chip select signal of MIO Bus st for the 1 external UART channel.
SB16C1053APCI PCI Target Controller with 2 Serial, 1 Parallel and MIO Bus PCI to 2S+1P with MIO Bus Bridge JULY 2013 REV 1.06 7. Configuration Loader SB16C1053APCI can perform system initialization by reading PCI Configuration header data from Internal MIO registers or external serial EEPROM. It is decided to download configuration header data through exist of external serial ROM. 2 SB16C1053APCI use a 256K I C serial EEPROM (24C256).
SB16C1053APCI PCI Target Controller with 2 Serial, 1 Parallel and MIO Bus PCI to 2S+1P with MIO Bus Bridge JULY 2013 REV 1.
SB16C1053APCI PCI Target Controller with 2 Serial, 1 Parallel and MIO Bus PCI to 2S+1P with MIO Bus Bridge JULY 2013 REV 1.06 8. PCI Configuration Space PCI Configuration offers one type of Configuration Space access method. - PCI Compatible Configuration method PCI Compatible Configuration method is compatible with PCI version 2.3 and higher and supports 100% binary compatibility to software for operating system agreed bus list and organization.
SB16C1053APCI PCI Target Controller with 2 Serial, 1 Parallel and MIO Bus PCI to 2S+1P with MIO Bus Bridge JULY 2013 REV 1.06 8.1.1 Vendor ID A 16-bit register which represents the manufacturer of the device. It is a unique ID given by PCI SIG after membership registration. If you do not own a Vendor ID, it is fine to use 14A1h given to SystemBase by PCI SIG. 8.1.2 Device ID A 16-bit unique ID of each device given by the Function Manufacturer which can be assigned by the manufacturer freely.
SB16C1053APCI PCI Target Controller with 2 Serial, 1 Parallel and MIO Bus PCI to 2S+1P with MIO Bus Bridge JULY 2013 REV 1.06 8.1.4 Status Register Table 8–4: Status Register Bit Type 15 RW Description Detected Parity Error: This bit must be set by the device whenever it detects a parity error, even if parity error handling is disabled. Default value of this bit is 0b. 14 RW Signaled System Error: This bit must be set whenever the device asserts SERR#.
SB16C1053APCI PCI Target Controller with 2 Serial, 1 Parallel and MIO Bus PCI to 2S+1P with MIO Bus Bridge JULY 2013 REV 1.06 8.1.5 Revision This register shows device revision. Manufacturer can assign it freely. It is also related to software device driver installation. 8.1.6 Class Code This register contains descriptions on functions the device implements. It is divided as Base Class, Sub Class and Programming Interface in bytes. It must be set to the values provided by PCI Bus Specification.
SB16C1053APCI PCI Target Controller with 2 Serial, 1 Parallel and MIO Bus PCI to 2S+1P with MIO Bus Bridge JULY 2013 REV 1.06 8.1.11 Base Address Registers These are spaces for assigning Base Address for accessing I/O device or memory on PCI Local Bus. There are 6 spaces Base Address Register from 0 to 5, but the Base Address Register 5 is set as unused and reserved area. When Base Address Register Bit[0] is 0b, the space is used as Memory space and when 1b, it is used as I/O space.
SB16C1053APCI PCI Target Controller with 2 Serial, 1 Parallel and MIO Bus PCI to 2S+1P with MIO Bus Bridge JULY 2013 REV 1.06 8.1.11.3 Base Address register 2 When SB16C1053APCI is in 1P and 2S1P mode, Base Address Register2(BAR2) automatically sets the size of the Address Space of Parallel Port Register. The I/O address space is 00~07h. When SB16C1053APCI is in 4S mode, Base Address Register2(BAR2) automatically rd sets the size of the Address Space of an external UART (3 UART) Register.
SB16C1053APCI PCI Target Controller with 2 Serial, 1 Parallel and MIO Bus PCI to 2S+1P with MIO Bus Bridge JULY 2013 REV 1.06 8.2 Power Management Registers of SB16C1053APCI Sometimes control over power is needed on PCI Bus applied systems. Especially in cases when system uses independent power source like mobile system or when PCI device uses a lot of power, the system must limit power supply to PCI device when it is not in use to make a power efficient system.
SB16C1053APCI PCI Target Controller with 2 Serial, 1 Parallel and MIO Bus PCI to 2S+1P with MIO Bus Bridge JULY 2013 REV 1.06 8.2.4 Power Management Control/Status Register (44~45h) This 16bit Register manages PCI Function’s Power Management state and it is also used to enable and monitor PME. Table 8–9: Power Management Control/Status Register Bit Type Description 15 RW PME_Status: This bit is set when the function would assert the PME# signal independent of the state of the PME_En bit.
SB16C1053APCI PCI Target Controller with 2 Serial, 1 Parallel and MIO Bus PCI to 2S+1P with MIO Bus Bridge JULY 2013 REV 1.06 9. Power Management PCI was the most famous and useful bus since it was introduced in 1992. It is used in various computer systems from Laptops to Servers. It supported high performance applications by offering large bandwidth and efficiently supporting multiple masters.
SB16C1053APCI PCI Target Controller with 2 Serial, 1 Parallel and MIO Bus PCI to 2S+1P with MIO Bus Bridge JULY 2013 REV 1.06 Power On Reset D0 Uninitialized PCI RST# Sof t Reset D0 Active D2 D3cold D1 Figure 9–1: D3 hot Vcc Remov ed PCI Function Power Management State Transition Cf. Hibernate state is variation of shutdown state. In this state, all states of computer is saved on disk and thus when power comes back, it can be started as current session. 9.
SB16C1053APCI PCI Target Controller with 2 Serial, 1 Parallel and MIO Bus PCI to 2S+1P with MIO Bus Bridge JULY 2013 REV 1.06 9.2.2 SB16C1053APCI Power Management Wakeup implementation Below figure is Logic Diagram of MAX3243. As you can see from this figure, RIN2 input signal (this pin is mainly prepared to be used by Ring Indicator.) is forked to reversed output signal called ROUT2 and output called ROUT2B.
SB16C1053APCI PCI Target Controller with 2 Serial, 1 Parallel and MIO Bus PCI to 2S+1P with MIO Bus Bridge JULY 2013 REV 1.06 10. Option I/O Space Option I/O Space is determined by Base Address Register 4 (20h ~ 23h) from PCI Configuration Space. Contents of I/O register which is installed in this area include basic information about PCI Multi Port hardware. The size of this area is 64(00h ~ 3Fh) bytes total.
SB16C1053APCI PCI Target Controller with 2 Serial, 1 Parallel and MIO Bus PCI to 2S+1P with MIO Bus Bridge JULY 2013 REV 1.06 10.1 General Information Register 0 – Serial Port Number (GIR0, BAR4+0h) Serial Port Number: Shows how many ports are installed on current Serial Multi-Port. 1S mode has 01h(1 port). 2S and 2S1P mode have 02h(2 ports). 4S mode have 04h (4 ports). 6S mode have 06h (6 ports). Other mode except upper cases have 00h. 10.
SB16C1053APCI PCI Target Controller with 2 Serial, 1 Parallel and MIO Bus PCI to 2S+1P with MIO Bus Bridge JULY 2013 REV 1.06 10.7 Interface Information Register 0, 1 (IIR0, BAR4+8h/ IIR1, BAR4+9h) IIR0 indicates interface information of serial ports in the Serial 1-port, Serial 2-port, Serial 4-port and Serial 6-port modes. In these modes, IIR1 is not used.
SB16C1053APCI PCI Target Controller with 2 Serial, 1 Parallel and MIO Bus PCI to 2S+1P with MIO Bus Bridge JULY 2013 REV 1.06 Table 10–5: Interface Information Register 1 Description Bit Symbol Description 7 IIR1[7] Hardwired to ‘0’ 6:4 IIR1[6:4] Interface Type Indicator: This interface information is set by INTF1[2:0] inputs. 000b: RS232 interface is selected. 100b: RS422 1:1 interface is selected. 101b: RS422 Multi-Drop interface is selected. 110b: RS485 Non-Echo interface is selected.
SB16C1053APCI PCI Target Controller with 2 Serial, 1 Parallel and MIO Bus PCI to 2S+1P with MIO Bus Bridge JULY 2013 REV 1.06 10.8 Interrupt Mask Register (IMR, BAR4+Ch) IMR enables or disables interrupt of serial ports and parallel port. Table 10–7: Interrupt Mask Register Description Bit Symbol Description 7 IMR[7] Not used. 6 IMR[6] Interrupt Masking Bit for Parallel Port 0b: Disables Parallel Port interrupt. (default) 1b: Enables Parallel Port interrupt.
SB16C1053APCI PCI Target Controller with 2 Serial, 1 Parallel and MIO Bus PCI to 2S+1P with MIO Bus Bridge JULY 2013 REV 1.06 10.9 Interrupt Poll Register (IPR, BAR4+10h) IPR indicates interrupt generation state of Port 1 ~ Port 2. Table 10–8: Interrupt Poll Register Description Bit Symbol Description 7 IPR[7] Not used. 6 IPR[6] Interrupt Polling Bit for Parallel Port 0b: Parallel Port interrupt has occurred. 1b: Parallel Port interrupt has not occurred.
SB16C1053APCI PCI Target Controller with 2 Serial, 1 Parallel and MIO Bus PCI to 2S+1P with MIO Bus Bridge JULY 2013 REV 1.06 10.10 Parallel Port FIFO TX Threshold Register (PPFTTR, BAR4+14h) Select the TX FIFO threshold of Parallel Port in ECP mode. Table 10–9: Parallel Port FIFO TX Threshold Register Description Bit Symbol Description 7:4 PPFTTR[7:4] Reserved. 3:0 PPFTTR[3:0] Select TX FIFO threshold of Parallel Port in ECP from 0 to 15. 10.
SB16C1053APCI PCI Target Controller with 2 Serial, 1 Parallel and MIO Bus PCI to 2S+1P with MIO Bus Bridge JULY 2013 REV 1.06 10.13 Parallel Port Interrupt Status Register (PPISR, BAR4+17h) It indicates interrupt status of parallel port. Table 10–12: Parallel Port Interrupt Status Register Description Bit Symbol Description 7:5 PPISR[7:5] Reserved. Hardwired to 000b.
SB16C1053APCI PCI Target Controller with 2 Serial, 1 Parallel and MIO Bus PCI to 2S+1P with MIO Bus Bridge JULY 2013 REV 1.06 10.14 PM_PME Message Resource Register (PPMRR, BAR4+18h) Select event signal to wakeup Root Complex in D3hot state. Table 10–13: PME# Signal Resource Register Description Bit Symbol Description 1 PSRR[1] D3hot-I 0b: Interrupt is not selected as Wakeup Event for waking up Root Complex (default). 1b: Interrupt is selected as Wakeup Event for waking up Root Complex.
SB16C1053APCI PCI Target Controller with 2 Serial, 1 Parallel and MIO Bus PCI to 2S+1P with MIO Bus Bridge JULY 2013 REV 1.06 10.15 General Purpose Outputs Control Register (GPOCR, BAR4+20h) GPOCR enables or disables GPO[7:0] to output ports respectively. Table 10–14: GPIO Output Enable Register Description Bit Symbol Description 7 GPOCR[7] 0b: DIR or MA0 isn’t output through DIR_INTF12_MA0 pin. (default). 1b: DIR or MA0 is output through DIR_INTF12_MA0 pin.
SB16C1053APCI PCI Target Controller with 2 Serial, 1 Parallel and MIO Bus PCI to 2S+1P with MIO Bus Bridge JULY 2013 REV 1.06 10.16 General Purpose Outputs Data Register (GPODR, BAR4+21h) GPODR sets output value of GPO[1:0] respectively. Table 10–15: General Purpose Outputs Data Register Description Bit Symbol Description 1 GPODR[1] The output value of GPO1 pin. 0 GPODR[0] The output value of GPO0 pin.
SB16C1053APCI PCI Target Controller with 2 Serial, 1 Parallel and MIO Bus PCI to 2S+1P with MIO Bus Bridge JULY 2013 REV 1.06 11. UART(SB16C1050A) Functional Description SB16C1050A offers 16C450 and 16C650 modes. When FIFO is enabled, it has a register configuration compatible with 64-byte FIFO and 16C650, so it becomes compatible with 16C650. If you enable 256-byte FIFO, you use the unique supreme function that SB16C1050A offers. It offers communication speed up to 5.
SB16C1053APCI PCI Target Controller with 2 Serial, 1 Parallel and MIO Bus PCI to 2S+1P with MIO Bus Bridge JULY 2013 REV 1.06 And by FCR[5:4], XOFF Trigger Level can be selected to either 8, 16, 56, or 60, and XON Trigger Level to either 0, 8, 16, or 56 by FCR[7:6]. You can verify XON and XOFF Trigger Level by FUR and FLR. In 64-byte FIFO mode TTR and RTR are Read Only. If you select 256-byte FIFO mode, you can experience more powerful features of SB16C1050A.
SB16C1053APCI PCI Target Controller with 2 Serial, 1 Parallel and MIO Bus PCI to 2S+1P with MIO Bus Bridge JULY 2013 REV 1.06 1b, too. When IER[6] is set to 1b and RTS# is changed from 0b to 1b by Auto-RTS function, interrupt occurs and it is displayed on ISR[5:0]. Interrupts by Auto-RTS function are removed if MSR is read. RTS# is changed from 0b to 1b after the first STOP bit is received. Figure 11–1 shows the RTS# timing chart while Auto-RTS is enabled.
SB16C1053APCI PCI Target Controller with 2 Serial, 1 Parallel and MIO Bus PCI to 2S+1P with MIO Bus Bridge JULY 2013 REV 1.06 11.3 Software Flow Control Software flow control is performed by Xon and Xoff character transmitting/accepting. Software flow control is enabled/disabled independently by programming EFR[3:0] and MCR[6:5, 2].
SB16C1053APCI PCI Target Controller with 2 Serial, 1 Parallel and MIO Bus PCI to 2S+1P with MIO Bus Bridge JULY 2013 REV 1.06 11.3.1 Transmit Software Flow Control To make Transmit Software Flow Control enabled, EFR[3:2] must be set to 01b, 10b or 11b. Unlike Auto-RTS in which 0b is outputted on RTS# when TX software flow control function is enabled, Xon character is not transmitted at first.
SB16C1053APCI PCI Target Controller with 2 Serial, 1 Parallel and MIO Bus PCI to 2S+1P with MIO Bus Bridge JULY 2013 REV 1.06 character. ■ If Xon and Xoff character are set to same, both characters are treated as Xon character. Tips for using Xon/Xoff character as two characters are as follows. ■ If received characters are Xon1, Xon1 and Xon2, RX flow control status becomes XON and previous Xon1 is ignored.
SB16C1053APCI PCI Target Controller with 2 Serial, 1 Parallel and MIO Bus PCI to 2S+1P with MIO Bus Bridge JULY 2013 REV 1.06 Table 11–3: Xon/Xoff Character Recognition Logic Table Xon1 Char. Xon2 Char. Xoff1 Char. Xoff2 Char. Recognition of Recognition of 11h 11h 13h 13h Xon Char. Xoff Char.
SB16C1053APCI PCI Target Controller with 2 Serial, 1 Parallel and MIO Bus PCI to 2S+1P with MIO Bus Bridge JULY 2013 REV 1.06 11.3.3 Xon Any Function While RX Software flow control function is enabled, data in TX FIFO are transmitted when received Xon character and transmission is suspended when Xoff character is received. This status is called ‘XOFF status’.
SB16C1053APCI PCI Target Controller with 2 Serial, 1 Parallel and MIO Bus PCI to 2S+1P with MIO Bus Bridge JULY 2013 REV 1.06 11.4 Sleep Mode with Auto Wake-Up The SB16C1050A provides sleep mode operation to reduce its power consumption when sleep mode is activated. Sleep mode is enabled when EFR[4] and IER[4] are set to 1b. Sleep mode is activated when: ■ RXD input is in idle state. ■ CTS#, DSR#, DCD#, and RI# are not toggling. ■ The TX FIFO and TSR are in empty state.
SB16C1053APCI PCI Target Controller with 2 Serial, 1 Parallel and MIO Bus PCI to 2S+1P with MIO Bus Bridge JULY 2013 REV 1.06 DLL and DLM must be written in order to program the baud rate. DLL and DLM are the least and most significant byte of the baud rate divisor, respectively. If DLL and DLM are both zero, the SB16C1050A is effectively disabled, as no baud clock will be generated. Table 11–4 shows the baud rate and divisor value for prescaler with divide by 1 as well as crystal with frequency 1.
SB16C1053APCI PCI Target Controller with 2 Serial, 1 Parallel and MIO Bus PCI to 2S+1P with MIO Bus Bridge JULY 2013 REV 1.06 External Clock XIN XIN R1 SB16C1052PCI Optional Clock Output SB16C1052PCI R2 XOUT XOUT C1 Figure 11–3: Table 11–5: CRYSTAL C2 Crystal Clock Circuit Reference Diagram Component Values Frequency Range (MHz) C1 (pF) C2 (pF) R1 (Ω) R2(Ω) 1.8~8 22 68 220K 470 ~ 1.5K 8~16 33~68 33 ~ 68 220K ~ 2.2M 470 ~ 1.5K 11.
SB16C1053APCI PCI Target Controller with 2 Serial, 1 Parallel and MIO Bus PCI to 2S+1P with MIO Bus Bridge JULY 2013 REV 1.06 TX FIFO TSR Output M S R Character #2 Character #1 16X Clock L S R M S R MCR[6] = 0 Transmitter Shift Register(TSR) MCR[6] = 0 M S R MCR[6] = 1 Brake Condition Output L S R MCR[6] = 0 L S R TXD PIN MCR[6] = 1 Figure 11–4: Break Condition Block Diagram 11.
SB16C1053APCI PCI Target Controller with 2 Serial, 1 Parallel and MIO Bus PCI to 2S+1P with MIO Bus Bridge JULY 2013 REV 1.06 Figure 11–6: Multi-Drop System Network The slave reads all data from bus and compares all data with address itself. If it is equal to address of slave, the slave accept the data. Then, because the slave doesn’t know what data from slave is address or data, comparison between data and its own address is operated to find a packet indicated its own among the data from bus.
SB16C1053APCI PCI Target Controller with 2 Serial, 1 Parallel and MIO Bus PCI to 2S+1P with MIO Bus Bridge JULY 2013 REV 1.06 Figure 11–7: 9-bit Communication on Multi-Drop System Network When RS422/RS485 communication is worked, slaves check the data from the master. If the address is same to its own address, the slave accepts following data and it is not same to its own address, the slave doesn’t accept the data.
SB16C1053APCI PCI Target Controller with 2 Serial, 1 Parallel and MIO Bus PCI to 2S+1P with MIO Bus Bridge JULY 2013 REV 1.06 The below picture is UART transmission using THR like the existing 16C550 UART. Transmit Holding Register Data Byte (THR) M S B Transmit Shift Register (TSR) Figure 11–8: L S B THR & TSR of transmit part But MDR(Multi-Drop mode Register)’s MDE(Multi-Drop mode Enable) bit is set, SB16C1050A is worked as Multi-Drop mode, this can 9-bit serial data transmission.
SB16C1053APCI PCI Target Controller with 2 Serial, 1 Parallel and MIO Bus PCI to 2S+1P with MIO Bus Bridge JULY 2013 REV 1.06 In general system to support 9-bit communication, when serial data is sent, software command procedure is like below.
SB16C1053APCI PCI Target Controller with 2 Serial, 1 Parallel and MIO Bus PCI to 2S+1P with MIO Bus Bridge JULY 2013 REV 1.06 th If 9 bit is checked for ‘1’ through 9-bit communication, it is regarded as address, it can be differentiated whether packet for right slave if it is compared to slave device. Generally, this comparison is worked in software level, but SB16C1050A UART Core provides this th comparison function to operate in hardware level.
SB16C1053APCI PCI Target Controller with 2 Serial, 1 Parallel and MIO Bus PCI to 2S+1P with MIO Bus Bridge JULY 2013 REV 1.06 12. UART Register Descriptions Each UART channel in the SB16C1050A has its own set of registers selected by address lines A2, A1, and A0 with a specific channel selected. The complete register set is shown on Table 12–1 and Table 12–2.
SB16C1053APCI PCI Target Controller with 2 Serial, 1 Parallel and MIO Bus PCI to 2S+1P with MIO Bus Bridge JULY 2013 REV 1.
SB16C1053APCI PCI Target Controller with 2 Serial, 1 Parallel and MIO Bus PCI to 2S+1P with MIO Bus Bridge JULY 2013 REV 1.
SB16C1053APCI PCI Target Controller with 2 Serial, 1 Parallel and MIO Bus PCI to 2S+1P with MIO Bus Bridge JULY 2013 REV 1.
SB16C1053APCI PCI Target Controller with 2 Serial, 1 Parallel and MIO Bus PCI to 2S+1P with MIO Bus Bridge JULY 2013 REV 1.06 5h 6h 7h RTR FUR FLR Bit 7 Bit 7 Bit 7 Bit 6 Bit 6 Bit 6 Bit 5 Bit 5 Bit 5 Bit 4 Bit 4 Bit 4 Bit 3 Bit 3 Bit 3 Bit 2 Bit 2 Bit 2 Bit 1 Bit 1 Bit 1 Bit 0 Bit 0 Bit 0 12.1 Transmit Holding Register (THR, Page 0) The transmitter section consists of the Transmit Holding Register (THR) and Transmit Shift Register (TSR). The THR is actually a 64-byte FIFO or a 256-byte FIFO.
SB16C1053APCI PCI Target Controller with 2 Serial, 1 Parallel and MIO Bus PCI to 2S+1P with MIO Bus Bridge JULY 2013 REV 1.06 4 IER[4] Sleep Mode Enable (Requires EFR[4] = 1): 0b: Disable sleep mode (default). 1b: Enable sleep mode. 3 IER[3] Modem Status Interrupt Enable: 0b: Disable the modem status register interrupt (default). 1b: Enable the modem status register interrupt. 2 IER[2] Receive Line Status Interrupt Enable: 0b: Disable the receive line status interrupt (default).
SB16C1053APCI PCI Target Controller with 2 Serial, 1 Parallel and MIO Bus PCI to 2S+1P with MIO Bus Bridge JULY 2013 REV 1.06 Table 12–4: Interrupt Status Register Description…continued Bit Interrupt Priority List and Reset Functions 5:0 Priority Interrupt Type Interrupt Source Interrupt Reset Control 00_0001 ― None None ― 00_0110 1 Receiver Line Status OE, PE, FE, BI Readi g the LSR.
SB16C1053APCI PCI Target Controller with 2 Serial, 1 Parallel and MIO Bus PCI to 2S+1P with MIO Bus Bridge JULY 2013 REV 1.06 This bit will return to 0b after resetting FIFO. 1 FCR[1] RX FIFO Reset: 0b: No RX FIFO reset (default) 1b: Reset RX FIFO pointers and RX FIFO level counter logic. This bit will return to 0b after resetting FIFO. 0 FCR[0] FIFO enable: 0b: Disable the TX and RX FIFO (default). 1b: Enable the TX and RX FIFO 12.
SB16C1053APCI PCI Target Controller with 2 Serial, 1 Parallel and MIO Bus PCI to 2S+1P with MIO Bus Bridge JULY 2013 REV 1.06 12.7 Modem Control Register (MCR, Page 0) MCR controls the interface with the modem, data set, or peripheral device that is emulating the modem. Table 12–7 shows MCR bit settings. Table 12–7: Modem Control Register Description Bit Symbol Description 7 MCR[7] Clock Prescaler Select: 0b: Divide by 1 clock input (default). 6 MCR[6] 1b: Divide by 4 clock input.
SB16C1053APCI PCI Target Controller with 2 Serial, 1 Parallel and MIO Bus PCI to 2S+1P with MIO Bus Bridge JULY 2013 REV 1.06 12.8 Line Status Register (LSR, Page 0) LSR provides the status of data transfers between the UART and the CPU. When LSR is read, LSR[4:2] reflect the error bits (BI, FE, PE) of the character at the top of the RX FIFO. The errors in a character are identified by reading LSR and then reading RBR. Reading LSR does not cause an increment of the RX FIFO read pointer.
SB16C1053APCI PCI Target Controller with 2 Serial, 1 Parallel and MIO Bus PCI to 2S+1P with MIO Bus Bridge JULY 2013 REV 1.06 12.9 Auto Toggle Control Register (ACR, Page 0 & Page 1) Address 5h is used for LSR (Line Status Register) in the existent UART Core with R/W permission. But we change to use address 5h with write permission to ACR (Auto Toggle Control Register). Originally we use ATR (Auto Toggle Register) in page 3 for the setting of auto toggling.
SB16C1053APCI PCI Target Controller with 2 Serial, 1 Parallel and MIO Bus PCI to 2S+1P with MIO Bus Bridge JULY 2013 REV 1.06 3 ∆DCD Input Status: MSR[3] 0b: No change on CD# input (default). 1b: Indicates th t the DCD# input has changed state. 2 ∆RI Input Status: MSR[2] 0b: No change on RI# input (default). 1b: Indicates that the RI# input has changed state from 0b to 1b. 1 ∆DSR Input Status: MSR[ ] 0b: No change on DSR# input (deault). 1b: Indicates that the DSR# input has changed state.
SB16C1053APCI PCI Target Controller with 2 Serial, 1 Parallel and MIO Bus PCI to 2S+1P with MIO Bus Bridge JULY 2013 REV 1.06 12.12 Scratch Pad Register (SPR, Page 0) This 8-bit Read/Write Register does not control the UART in anyway. It is intended as a scratch pad register to be used by the programmer to hold data temporarily. 12.13 Transmit 9-bit Address Register (TAR, Page 0) Address 7h is used for SPR (Scratch Pad Register) in the existent UART Core with R/W permission.
SB16C1053APCI PCI Target Controller with 2 Serial, 1 Parallel and MIO Bus PCI to 2S+1P with MIO Bus Bridge JULY 2013 REV 1.06 12.17 Flow Control Status Register (FSR, Page 2) FSR show the status of operation of TX Hardware Flow Control, RX Hardware Flow Control, TX Software Flow Control, and RX Software Flow Control. Table 12–12: Flow Control Status Register Description Bit Symbol Description 7:6 FSR[7:6] Not used, always 00b.
SB16C1053APCI PCI Target Controller with 2 Serial, 1 Parallel and MIO Bus PCI to 2S+1P with MIO Bus Bridge JULY 2013 REV 1.06 0b: When FIFO or Auto-CTS flow control is disabled. If FIFO and Auto-CTS flow control is enabled, 0b is inputted in CTS# pin and it means external device can receive more data. This time data in TX FIFO are transmitted. 1b: If FIFO and Auto-CTS flow control is enabled, 1b is inputted in CTS# pin and it means external device can not receive more data.
SB16C1053APCI PCI Target Controller with 2 Serial, 1 Parallel and MIO Bus PCI to 2S+1P with MIO Bus Bridge JULY 2013 REV 1.06 Table 12–14: Auto Toggle Control Register Description Bit Symbol Description 7 ATR[7] RXEN# Polarity Select: 0b: Asserted output of RXEN# is 0b. 1b: Asserted output of RXEN# is 1b. (default) 6 ATR[6] RXEN# Enable 0b: RXEN# is outputted as same as ATR[7], irrespective of TXD signal. (default) 1b: RXEN# is outputted as same as ATR[7] when TXD signal is not transmitting.
SB16C1053APCI PCI Target Controller with 2 Serial, 1 Parallel and MIO Bus PCI to 2S+1P with MIO Bus Bridge JULY 2013 REV 1.06 12.20 Enhanced Feature Register (EFR, Page 3) EFR enables or disables the enhanced features of the UART. Table 12–15 shows EFR bit settings. Table 12–15: Enhanced Feature Register Description Bit Symbol Description 7 EFR[7] Auto-CTS Flow Control Enable: 0b: Auto-CTS flow control is disabled (default). 1b: Auto-CTS flow control is enabled.
SB16C1053APCI PCI Target Controller with 2 Serial, 1 Parallel and MIO Bus PCI to 2S+1P with MIO Bus Bridge JULY 2013 REV 1.06 12.21 Special Character Register (SCR, Page 3) When Bit0 of MDR is set to ‘1’ (9-bit transmission mode), Xoff2 register is used as Special Character Register. 12.22 Additional Feature Register (AFR, Page 4) AFR enables or disables the 256-byte FIFO mode and controls the global interrupt. Table 12–16 shows AFR bit settings.
SB16C1053APCI PCI Target Controller with 2 Serial, 1 Parallel and MIO Bus PCI to 2S+1P with MIO Bus Bridge JULY 2013 REV 1.06 12.25 Receive FIFO Trigger Level Register (RTR, Page 4) RTR operates only when 256-byte FIFO mode is enabled. It sets the trigger level of 256-byte RX FIFO for generating receive interrupt. Interrupt is generated when the number of data remained in RX FIFO exceeds the value of RTR(this time, timeout or interrupt is valid). Initial value is 80h, 1000_0000b.
SB16C1053APCI PCI Target Controller with 2 Serial, 1 Parallel and MIO Bus PCI to 2S+1P with MIO Bus Bridge JULY 2013 REV 1.06 13. Parallel Port Description SB16C1053APCI offers one Parallel Port supporting Compatibility/Nibble/Byte/EPP/ECP modes. The Parallel Port complies with IEEE standard 1284. And it is host-based multi-function parallel port that be to transfer data between a host PC and a peripheral such as printers, scanners and external drives.
SB16C1053APCI PCI Target Controller with 2 Serial, 1 Parallel and MIO Bus PCI to 2S+1P with MIO Bus Bridge JULY 2013 REV 1.06 13.2 Compatibility Mode Compatibility mode provides an asynchronous, byte wide, forward channel (host-to-peripheral), with the data and status lines used according to original definitions, as per the original Centronics port. It is also known as SPP, industry Standard Parallel Port. 13.2.
SB16C1053APCI PCI Target Controller with 2 Serial, 1 Parallel and MIO Bus PCI to 2S+1P with MIO Bus Bridge JULY 2013 REV 1.06 13.2.
SB16C1053APCI PCI Target Controller with 2 Serial, 1 Parallel and MIO Bus PCI to 2S+1P with MIO Bus Bridge JULY 2013 REV 1.06 13.3 Nibble Mode Nibble mode provides an asynchronous, reverse channel(peripheral-to-host) under the control of the host. Data bytes are transmitted as two sequential, four-bit nibbles using four peripheral-tohost status lines.
SB16C1053APCI PCI Target Controller with 2 Serial, 1 Parallel and MIO Bus PCI to 2S+1P with MIO Bus Bridge JULY 2013 REV 1.06 13.4 Byte Mode BYTE MODE provides an asynchronous, byte wide, reverse channel (peripheral-to-host) using the eight data lines of the interface for data and the control/status lines for handshaking.
SB16C1053APCI PCI Target Controller with 2 Serial, 1 Parallel and MIO Bus PCI to 2S+1P with MIO Bus Bridge JULY 2013 REV 1.06 13.5 EPP Mode ENHANCED PARALLEL PORT (EPP) MODE provides an asynchronous, byte wide, bi-irectional channel controlled by the host device. This mode provides separate address and data cycles over the eight data lines of the interface. The Enhanced Parallel Port (EPP) was designed in a joint venture between Intel, Xircom & Zenith Data Systems.
SB16C1053APCI PCI Target Controller with 2 Serial, 1 Parallel and MIO Bus PCI to 2S+1P with MIO Bus Bridge JULY 2013 REV 1.06 13.5.
SB16C1053APCI PCI Target Controller with 2 Serial, 1 Parallel and MIO Bus PCI to 2S+1P with MIO Bus Bridge JULY 2013 REV 1.06 13.6.1 Pin Descriptions in the ECP Mode Table 13–11: Signal Name Pin Description in ECP Mode Type ECP Protocol Signal Description Host Clock (HostClk): SB16C1053APCI assert HostClk to instruct the peripheral to latch the data on PD[7:0] in forward direction. The peripheral latch data on the rising edge of HostClk. HostClk nSTROBE O handshake with PeriphAck.
SB16C1053APCI PCI Target Controller with 2 Serial, 1 Parallel and MIO Bus PCI to 2S+1P with MIO Bus Bridge JULY 2013 REV 1.06 13.6.2 Register Descriptions in the ECP Mode Table 13–12: Address Basic Parallel Port Registers in ECP Mode Abbreviation Register Name ECR[7:5] Access 0h ECPAFIFO ECP Address 011 R/W 1h STAT Status Register ALL R 2h CTRL Control Register ALL R/W (BAR2 +) The ECPAFIFO register provides a channel address to the peripheral depending on the state of bit 7.
SB16C1053APCI PCI Target Controller with 2 Serial, 1 Parallel and MIO Bus PCI to 2S+1P with MIO Bus Bridge JULY 2013 REV 1.06 port data lines, but without any hardware handshake. The Test FIFO does not stall when overwritten or underrun. Data is simply ignored or re-read. The full and empty bits of the ECR register (bits 1 and 0) can however be used to ascertain the correct state of the FIFO. The CFGA register provides information about the ECP Mode implementation. It is a Read Only register.
SB16C1053APCI PCI Target Controller with 2 Serial, 1 Parallel and MIO Bus PCI to 2S+1P with MIO Bus Bridge JULY 2013 REV 1.06 101 Reserved. This selects an ECP Test Mode in which the FIFO is read and written purely 110 through the microprocessor interface. This is places the interface into Configuration Mode. In this mode, the CFGA 111 and CFGB registers are accessible at 0h & 1h of BAR3 respectively.
SB16C1053APCI PCI Target Controller with 2 Serial, 1 Parallel and MIO Bus PCI to 2S+1P with MIO Bus Bridge JULY 2013 REV 1.06 bit commands. When in the forward direction, normal data is transferred when nAUTOFD is high and an 8-bit command is transferred when nAUTOFD is low. When in the reverse direction, normal data is transferred when BUSY is high and an 8-bit command is transferred when BUSY is low. 13.6.
SB16C1053APCI PCI Target Controller with 2 Serial, 1 Parallel and MIO Bus PCI to 2S+1P with MIO Bus Bridge JULY 2013 REV 1.06 14. MIO Bus Description SB16C1053APCI can extend to 2 serial ports or 4 serial ports additionally using external UART. Because SB16C1053APCI have multi-function pins, some pins works as MIO Bus TM signals when SB16C16C1053APCI is in 4S mode or 6S mode.
SB16C1053APCI PCI Target Controller with 2 Serial, 1 Parallel and MIO Bus PCI to 2S+1P with MIO Bus Bridge JULY 2013 REV 1.06 Table 14–1: TM Pin Description of MIO Bus Signal Name Pin No. I/O MD[0] 86 I/O Signal Description 8-bit Data Bus of MIO Bus MD[1] 83 I/O It used for exchange 8-bit data between UART MD[2] 82 I/O and SB16C1053APCI.
SB16C1053APCI PCI Target Controller with 2 Serial, 1 Parallel and MIO Bus PCI to 2S+1P with MIO Bus Bridge JULY 2013 REV 1.06 14.2 Interfacing between SB16C1053APCI and Quad-UART When you make the interfacing between SB16C1053APCI and SB16C554A, please refer below figure.
SB16C1053APCI PCI Target Controller with 2 Serial, 1 Parallel and MIO Bus PCI to 2S+1P with MIO Bus Bridge JULY 2013 REV 1.06 15. UART Programmer’s Guide The base set of registers that is used during high-speed data transfer has a straightforward access method. The extended function registers require special access bits to be decoded along with the address lines. The following guide will help with programming these registers. Note that the descriptions below are for individual register access.
SB16C1053APCI PCI Target Controller with 2 Serial, 1 Parallel and MIO Bus PCI to 2S+1P with MIO Bus Bridge JULY 2013 REV 1.
SB16C1053APCI PCI Target Controller with 2 Serial, 1 Parallel and MIO Bus PCI to 2S+1P with MIO Bus Bridge JULY 2013 REV 1.
SB16C1053APCI PCI Target Controller with 2 Serial, 1 Parallel and MIO Bus PCI to 2S+1P with MIO Bus Bridge JULY 2013 REV 1.06 16. Electrical Information 16.1 Absolute Maximum Ratings Symbol Parameter Min Max Unit VDD DC Supply Voltage -0.5 7.0 V VIN Input Voltage -0.5 VDD+0.5 V VOUT Output Voltage Range 0 VDD+0.
SB16C1053APCI PCI Target Controller with 2 Serial, 1 Parallel and MIO Bus PCI to 2S+1P with MIO Bus Bridge JULY 2013 REV 1.06 II Input Current at Max Voltage 1mA 2.7V~3.6V Input=5.5V 17. Timing Specification 17.
SB16C1053APCI PCI Target Controller with 2 Serial, 1 Parallel and MIO Bus PCI to 2S+1P with MIO Bus Bridge JULY 2013 REV 1.06 V_Th CLK V_test T_su V_Tl T_h V_Th INPUT V_test inputs valid V_test V_Tl Figure 17-2: Symbol 3.3V Signaling Units Vth 0.6Vcc V Vtl 0.2Vcc V Vtest 0.4Vcc V Vtrise 0.285Vcc V Vtfall 0.615Vcc V Vmax 0.4Vcc V 1.
SB16C1053APCI PCI Target Controller with 2 Serial, 1 Parallel and MIO Bus PCI to 2S+1P with MIO Bus Bridge JULY 2013 REV 1.06 18. Package Outline 128Pin TQFP: Thin Quad Flat Package; Body 14ⅹ14ⅹ1.4 mm Note : All dimensions are in millimeters.
