DataSheet_SB16C1053APCI_v106

SB16C1053APCI
PCI Target Controller with 2 Serial, 1 Parallel and MIO Bus
PCI to 2S+1P with MIO Bus Bridge
JULY 2013 REV 1.06
13
6. Pin Configuration
6.1 Pin Configuration for 128-Pin TQFP Package
Figure 6–1: 128-Pin TQFP Pin Configuration
RXD0
DCD0#
WAKEREQ
SLCT_MIRQ3
TXD0
AD[7]
GND
PORT[1]_MCS2#
89
STOP#
C/BE[1]#
105
70
1
AD[27]
56
DSR0#
79
5
3
NC - No internal connection
54
AD[26] AD[29]
100
DTR1#
DSR1#
RSVD0/GPO[1]
PCI_33M#
PD4_MD[3]
PERR#
AD[5]
TXEN0_INTF0[0]
118
66
32
PME#
108 121
59
72
99
14
17
PD7_MD[6]
DTR0#
87
C/BE[3]#
MCS3#_OSC[2]
NC
28
CLK
GND
ACK#_MIRQ1
RTS0#
AD[14]
XTAL1
HOSTLOGIC_H_PORT[2]_MA[2]
22
AD[21]
77
88
103
64
83
RXEN0#_INTF0[1]
PD2_MD[1]
RI1#
IDSEL
AD[13]
42
NC
35
120
97
58 33
95
36
74
NC
126 112
18
RTS1#
GNT#
117
AD[1]
VCC
34
13
6
NC
82
61
16
11
123 109
15
55
GND
AD[8]
C/BE[0]#
INIT#_MRESET
AD[23]
AD[22]
50
85
VCC
RXD1
DCD1#
AD[31]
LOCK#
AD[11]
65
26
62
86
119
78
124 110
94
AD[30]
115
23
C/BE[2]#
PPERILOGICH_MA[1]_OSC[1]
DIR_INTF1[2]_MA[0]
57
2
51 41
76
122
60
PD1_MD[0]
TXD1
VCC
AD[15]
PD3_MD[2]
8
12
AD[24]
102
63
127 113
10
92
INTA#
SERR#
NC
VCC
GND
DEVSEL#
68
30
47 53
98
107 111
27
VCC
24
125
TXEN1_INTF1[0]
PORT[0]_MCS0#
VCC
AD[2]
EE_SCL
PAR
AD[10]
AD[3]
69
29
AD[18]
81
106 128
9
45
25
114
40 37 49
104
71
52
REQ#
PD8_MD[7]
PD5_MD[4]
GND
PE_MIRQ0
BUSY_MIRQ2
IRDY#
AD[6]
NC
7
91
FRAME#
4
19
RST# AD[28]
SB16C1053APCI-TQ
93
38
21
RI0#
48
20
CTS1#
CTS0#
VCC
XTAL2
EE_SDA
AD[16]
AD[4]
96
AD[20]
SLIN#
GND
GPO[0]
PMES_INTF0[2]
AFD#_MIOW#
AD[12]
GND
AD[0]
116
AD[19]
TRDY#
31
75
46
GND
67
84
73
39 43
GND NC
44
90
AD[25]
STB#_MIOR#_OSC[0]
ERR#_MCS1#
PD6_MD[5]
AD[9]
RXEN1#_INTF1[1]
101
80
AD[17]
VCC