DataSheet_SB16C1053APCI_v106

SB16C1053APCI
PCI Target Controller with 2 Serial, 1 Parallel and MIO Bus
PCI to 2S+1P with MIO Bus Bridge
JULY 2013 REV 1.06
19
Table 6–1: Pin Description…continued
PCI Interfaces
Name
Pin
Type
Description
AD[31]
AD[30]
AD[29]
AD[28]
AD[27]
AD[26]
AD[25]
AD[24]
AD[23]
AD[22]
AD[21]
AD[20]
AD[19]
AD[18]
AD[17]
AD[16]
AD[15]
AD[14]
AD[13]
AD[12]
AD[11]
AD[10]
AD[09]
AD[08]
AD[07]
AD[06]
AD[05]
AD[04]
AD[03]
AD[02]
AD[01]
AD[00]
120,
123
124
125
126
127
128
1
4
5
6
7
8
9
10
11
25
26
27
28
29
30
31
32
34
35
36
37
40
41
42
43
T/S
Address and Data: These signals are multiplexed on the same pins. A Bus
transaction consists of an address phase followed by a data phase.
SB16C1053APCI does no support both read and write bursts.
C/BE[3]#
C/BE[2]#
C/BE[1]#
C/BE[0]#
2
12
24
33
T/S
Bus Command and Byte Enables: These signals are multiplexed on same
pins. During the address phase of transaction, C/BE[3:0]# define the bus
command. During the data phase, C/BE[3:0]# are used as Byte Enables.
LOCK#
20
S/T/S
Lock: This signal provides for exclusive use of a resource. SB16C1053APCI
may be locked by one master at a time. See the PCI Local Bus Specification
for the detail operation of lock function.