DataSheet_SB16C1053APCI_v106

SB16C1053APCI
PCI Target Controller with 2 Serial, 1 Parallel and MIO Bus
PCI to 2S+1P with MIO Bus Bridge
JULY 2013 REV 1.06
2
CONTENTS
1. Description ..................................................................................................................................... 7
2. Features ......................................................................................................................................... 7
2.1 PCI Interface .......................................................................................................................... 7
2.2 Internal Dual-UART ................................................................................................................. 7
2.3 Parallel Interface ..................................................................................................................... 8
2.4 MIO Bus Interface ................................................................................................................... 8
3. Ordering Information ....................................................................................................................... 8
4. Block Diagram ................................................................................................................................. 9
5. Applications .................................................................................................................................. 10
5.1 Serial 1-port (1S) .................................................................................................................. 10
5.2 Serial 2-port (2S) .................................................................................................................. 10
5.3 Serial 2-port and Parallel 1-port (2S 1P) ................................................................................. 11
5.4 Parallel 1-port (1P) ................................................................................................................ 11
5.5 Serial 4-port (4S) .................................................................................................................. 12
5.6 Serial 6-port (6S) .................................................................................................................. 12
6. Pin Configuration........................................................................................................................... 13
6.1 Pin Configuration for 128-Pin TQFP Package ........................................................................... 13
6.2 Pin Description ..................................................................................................................... 14
7. Configuration Loader ..................................................................................................................... 22
7.1 MIO Register ........................................................................................................................ 22
7.2 Serial EEPROM Information Table ........................................................................................... 22
8. PCI Configuration Space ................................................................................................................ 24
8.1 Configuration Space Map of SB16C1053APCI .......................................................................... 24
8.1.1 Vendor ID ................................................................................................................... 25
8.1.2 Device ID .................................................................................................................... 25
8.1.3 Command Register ...................................................................................................... 25
8.1.4 Status Register ............................................................................................................ 26
8.1.5 Revision ...................................................................................................................... 27
8.1.6 Class Code .................................................................................................................. 27
8.1.7 Cache Line Size ........................................................................................................... 27
8.1.8 Latency Timer ............................................................................................................. 27